1#ifndef CAPSTONE_ARM64_H
2#define CAPSTONE_ARM64_H
3
4/* Capstone Disassembly Engine */
5/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2015 */
6
7#ifdef __cplusplus
8extern "C" {
9#endif
10
11#include "platform.h"
12
13#ifdef _MSC_VER
14#pragma warning(disable:4201)
15#endif
16
17/// ARM64 shift type
18typedef enum arm64_shifter {
19 ARM64_SFT_INVALID = 0,
20 ARM64_SFT_LSL = 1,
21 ARM64_SFT_MSL = 2,
22 ARM64_SFT_LSR = 3,
23 ARM64_SFT_ASR = 4,
24 ARM64_SFT_ROR = 5,
25} arm64_shifter;
26
27/// ARM64 extender type
28typedef enum arm64_extender {
29 ARM64_EXT_INVALID = 0,
30 ARM64_EXT_UXTB = 1,
31 ARM64_EXT_UXTH = 2,
32 ARM64_EXT_UXTW = 3,
33 ARM64_EXT_UXTX = 4,
34 ARM64_EXT_SXTB = 5,
35 ARM64_EXT_SXTH = 6,
36 ARM64_EXT_SXTW = 7,
37 ARM64_EXT_SXTX = 8,
38} arm64_extender;
39
40/// ARM64 condition code
41typedef enum arm64_cc {
42 ARM64_CC_INVALID = 0,
43 ARM64_CC_EQ = 1, ///< Equal
44 ARM64_CC_NE = 2, ///< Not equal: Not equal, or unordered
45 ARM64_CC_HS = 3, ///< Unsigned higher or same: >, ==, or unordered
46 ARM64_CC_LO = 4, ///< Unsigned lower or same: Less than
47 ARM64_CC_MI = 5, ///< Minus, negative: Less than
48 ARM64_CC_PL = 6, ///< Plus, positive or zero: >, ==, or unordered
49 ARM64_CC_VS = 7, ///< Overflow: Unordered
50 ARM64_CC_VC = 8, ///< No overflow: Ordered
51 ARM64_CC_HI = 9, ///< Unsigned higher: Greater than, or unordered
52 ARM64_CC_LS = 10, ///< Unsigned lower or same: Less than or equal
53 ARM64_CC_GE = 11, ///< Greater than or equal: Greater than or equal
54 ARM64_CC_LT = 12, ///< Less than: Less than, or unordered
55 ARM64_CC_GT = 13, ///< Signed greater than: Greater than
56 ARM64_CC_LE = 14, ///< Signed less than or equal: <, ==, or unordered
57 ARM64_CC_AL = 15, ///< Always (unconditional): Always (unconditional)
58 ARM64_CC_NV = 16, ///< Always (unconditional): Always (unconditional)
59 //< Note the NV exists purely to disassemble 0b1111. Execution
60 //< is "always".
61} arm64_cc;
62
63/// System registers
64typedef enum arm64_sysreg {
65 // System registers for MRS
66 ARM64_SYSREG_INVALID = 0,
67 ARM64_SYSREG_MDCCSR_EL0 = 0x9808, // 10 011 0000 0001 000
68 ARM64_SYSREG_DBGDTRRX_EL0 = 0x9828, // 10 011 0000 0101 000
69 ARM64_SYSREG_MDRAR_EL1 = 0x8080, // 10 000 0001 0000 000
70 ARM64_SYSREG_OSLSR_EL1 = 0x808c, // 10 000 0001 0001 100
71 ARM64_SYSREG_DBGAUTHSTATUS_EL1 = 0x83f6, // 10 000 0111 1110 110
72 ARM64_SYSREG_PMCEID0_EL0 = 0xdce6, // 11 011 1001 1100 110
73 ARM64_SYSREG_PMCEID1_EL0 = 0xdce7, // 11 011 1001 1100 111
74 ARM64_SYSREG_MIDR_EL1 = 0xc000, // 11 000 0000 0000 000
75 ARM64_SYSREG_CCSIDR_EL1 = 0xc800, // 11 001 0000 0000 000
76 ARM64_SYSREG_CLIDR_EL1 = 0xc801, // 11 001 0000 0000 001
77 ARM64_SYSREG_CTR_EL0 = 0xd801, // 11 011 0000 0000 001
78 ARM64_SYSREG_MPIDR_EL1 = 0xc005, // 11 000 0000 0000 101
79 ARM64_SYSREG_REVIDR_EL1 = 0xc006, // 11 000 0000 0000 110
80 ARM64_SYSREG_AIDR_EL1 = 0xc807, // 11 001 0000 0000 111
81 ARM64_SYSREG_DCZID_EL0 = 0xd807, // 11 011 0000 0000 111
82 ARM64_SYSREG_ID_PFR0_EL1 = 0xc008, // 11 000 0000 0001 000
83 ARM64_SYSREG_ID_PFR1_EL1 = 0xc009, // 11 000 0000 0001 001
84 ARM64_SYSREG_ID_DFR0_EL1 = 0xc00a, // 11 000 0000 0001 010
85 ARM64_SYSREG_ID_AFR0_EL1 = 0xc00b, // 11 000 0000 0001 011
86 ARM64_SYSREG_ID_MMFR0_EL1 = 0xc00c, // 11 000 0000 0001 100
87 ARM64_SYSREG_ID_MMFR1_EL1 = 0xc00d, // 11 000 0000 0001 101
88 ARM64_SYSREG_ID_MMFR2_EL1 = 0xc00e, // 11 000 0000 0001 110
89 ARM64_SYSREG_ID_MMFR3_EL1 = 0xc00f, // 11 000 0000 0001 111
90 ARM64_SYSREG_ID_ISAR0_EL1 = 0xc010, // 11 000 0000 0010 000
91 ARM64_SYSREG_ID_ISAR1_EL1 = 0xc011, // 11 000 0000 0010 001
92 ARM64_SYSREG_ID_ISAR2_EL1 = 0xc012, // 11 000 0000 0010 010
93 ARM64_SYSREG_ID_ISAR3_EL1 = 0xc013, // 11 000 0000 0010 011
94 ARM64_SYSREG_ID_ISAR4_EL1 = 0xc014, // 11 000 0000 0010 100
95 ARM64_SYSREG_ID_ISAR5_EL1 = 0xc015, // 11 000 0000 0010 101
96 ARM64_SYSREG_ID_A64PFR0_EL1 = 0xc020, // 11 000 0000 0100 000
97 ARM64_SYSREG_ID_A64PFR1_EL1 = 0xc021, // 11 000 0000 0100 001
98 ARM64_SYSREG_ID_A64DFR0_EL1 = 0xc028, // 11 000 0000 0101 000
99 ARM64_SYSREG_ID_A64DFR1_EL1 = 0xc029, // 11 000 0000 0101 001
100 ARM64_SYSREG_ID_A64AFR0_EL1 = 0xc02c, // 11 000 0000 0101 100
101 ARM64_SYSREG_ID_A64AFR1_EL1 = 0xc02d, // 11 000 0000 0101 101
102 ARM64_SYSREG_ID_A64ISAR0_EL1 = 0xc030, // 11 000 0000 0110 000
103 ARM64_SYSREG_ID_A64ISAR1_EL1 = 0xc031, // 11 000 0000 0110 001
104 ARM64_SYSREG_ID_A64MMFR0_EL1 = 0xc038, // 11 000 0000 0111 000
105 ARM64_SYSREG_ID_A64MMFR1_EL1 = 0xc039, // 11 000 0000 0111 001
106 ARM64_SYSREG_MVFR0_EL1 = 0xc018, // 11 000 0000 0011 000
107 ARM64_SYSREG_MVFR1_EL1 = 0xc019, // 11 000 0000 0011 001
108 ARM64_SYSREG_MVFR2_EL1 = 0xc01a, // 11 000 0000 0011 010
109 ARM64_SYSREG_RVBAR_EL1 = 0xc601, // 11 000 1100 0000 001
110 ARM64_SYSREG_RVBAR_EL2 = 0xe601, // 11 100 1100 0000 001
111 ARM64_SYSREG_RVBAR_EL3 = 0xf601, // 11 110 1100 0000 001
112 ARM64_SYSREG_ISR_EL1 = 0xc608, // 11 000 1100 0001 000
113 ARM64_SYSREG_CNTPCT_EL0 = 0xdf01, // 11 011 1110 0000 001
114 ARM64_SYSREG_CNTVCT_EL0 = 0xdf02, // 11 011 1110 0000 010
115
116 // Trace registers
117 ARM64_SYSREG_TRCSTATR = 0x8818, // 10 001 0000 0011 000
118 ARM64_SYSREG_TRCIDR8 = 0x8806, // 10 001 0000 0000 110
119 ARM64_SYSREG_TRCIDR9 = 0x880e, // 10 001 0000 0001 110
120 ARM64_SYSREG_TRCIDR10 = 0x8816, // 10 001 0000 0010 110
121 ARM64_SYSREG_TRCIDR11 = 0x881e, // 10 001 0000 0011 110
122 ARM64_SYSREG_TRCIDR12 = 0x8826, // 10 001 0000 0100 110
123 ARM64_SYSREG_TRCIDR13 = 0x882e, // 10 001 0000 0101 110
124 ARM64_SYSREG_TRCIDR0 = 0x8847, // 10 001 0000 1000 111
125 ARM64_SYSREG_TRCIDR1 = 0x884f, // 10 001 0000 1001 111
126 ARM64_SYSREG_TRCIDR2 = 0x8857, // 10 001 0000 1010 111
127 ARM64_SYSREG_TRCIDR3 = 0x885f, // 10 001 0000 1011 111
128 ARM64_SYSREG_TRCIDR4 = 0x8867, // 10 001 0000 1100 111
129 ARM64_SYSREG_TRCIDR5 = 0x886f, // 10 001 0000 1101 111
130 ARM64_SYSREG_TRCIDR6 = 0x8877, // 10 001 0000 1110 111
131 ARM64_SYSREG_TRCIDR7 = 0x887f, // 10 001 0000 1111 111
132 ARM64_SYSREG_TRCOSLSR = 0x888c, // 10 001 0001 0001 100
133 ARM64_SYSREG_TRCPDSR = 0x88ac, // 10 001 0001 0101 100
134 ARM64_SYSREG_TRCDEVAFF0 = 0x8bd6, // 10 001 0111 1010 110
135 ARM64_SYSREG_TRCDEVAFF1 = 0x8bde, // 10 001 0111 1011 110
136 ARM64_SYSREG_TRCLSR = 0x8bee, // 10 001 0111 1101 110
137 ARM64_SYSREG_TRCAUTHSTATUS = 0x8bf6, // 10 001 0111 1110 110
138 ARM64_SYSREG_TRCDEVARCH = 0x8bfe, // 10 001 0111 1111 110
139 ARM64_SYSREG_TRCDEVID = 0x8b97, // 10 001 0111 0010 111
140 ARM64_SYSREG_TRCDEVTYPE = 0x8b9f, // 10 001 0111 0011 111
141 ARM64_SYSREG_TRCPIDR4 = 0x8ba7, // 10 001 0111 0100 111
142 ARM64_SYSREG_TRCPIDR5 = 0x8baf, // 10 001 0111 0101 111
143 ARM64_SYSREG_TRCPIDR6 = 0x8bb7, // 10 001 0111 0110 111
144 ARM64_SYSREG_TRCPIDR7 = 0x8bbf, // 10 001 0111 0111 111
145 ARM64_SYSREG_TRCPIDR0 = 0x8bc7, // 10 001 0111 1000 111
146 ARM64_SYSREG_TRCPIDR1 = 0x8bcf, // 10 001 0111 1001 111
147 ARM64_SYSREG_TRCPIDR2 = 0x8bd7, // 10 001 0111 1010 111
148 ARM64_SYSREG_TRCPIDR3 = 0x8bdf, // 10 001 0111 1011 111
149 ARM64_SYSREG_TRCCIDR0 = 0x8be7, // 10 001 0111 1100 111
150 ARM64_SYSREG_TRCCIDR1 = 0x8bef, // 10 001 0111 1101 111
151 ARM64_SYSREG_TRCCIDR2 = 0x8bf7, // 10 001 0111 1110 111
152 ARM64_SYSREG_TRCCIDR3 = 0x8bff, // 10 001 0111 1111 111
153
154 // GICv3 registers
155 ARM64_SYSREG_ICC_IAR1_EL1 = 0xc660, // 11 000 1100 1100 000
156 ARM64_SYSREG_ICC_IAR0_EL1 = 0xc640, // 11 000 1100 1000 000
157 ARM64_SYSREG_ICC_HPPIR1_EL1 = 0xc662, // 11 000 1100 1100 010
158 ARM64_SYSREG_ICC_HPPIR0_EL1 = 0xc642, // 11 000 1100 1000 010
159 ARM64_SYSREG_ICC_RPR_EL1 = 0xc65b, // 11 000 1100 1011 011
160 ARM64_SYSREG_ICH_VTR_EL2 = 0xe659, // 11 100 1100 1011 001
161 ARM64_SYSREG_ICH_EISR_EL2 = 0xe65b, // 11 100 1100 1011 011
162 ARM64_SYSREG_ICH_ELSR_EL2 = 0xe65d, // 11 100 1100 1011 101
163} arm64_sysreg;
164
165typedef enum arm64_msr_reg {
166 // System registers for MSR
167 ARM64_SYSREG_DBGDTRTX_EL0 = 0x9828, // 10 011 0000 0101 000
168 ARM64_SYSREG_OSLAR_EL1 = 0x8084, // 10 000 0001 0000 100
169 ARM64_SYSREG_PMSWINC_EL0 = 0xdce4, // 11 011 1001 1100 100
170
171 // Trace Registers
172 ARM64_SYSREG_TRCOSLAR = 0x8884, // 10 001 0001 0000 100
173 ARM64_SYSREG_TRCLAR = 0x8be6, // 10 001 0111 1100 110
174
175 // GICv3 registers
176 ARM64_SYSREG_ICC_EOIR1_EL1 = 0xc661, // 11 000 1100 1100 001
177 ARM64_SYSREG_ICC_EOIR0_EL1 = 0xc641, // 11 000 1100 1000 001
178 ARM64_SYSREG_ICC_DIR_EL1 = 0xc659, // 11 000 1100 1011 001
179 ARM64_SYSREG_ICC_SGI1R_EL1 = 0xc65d, // 11 000 1100 1011 101
180 ARM64_SYSREG_ICC_ASGI1R_EL1 = 0xc65e, // 11 000 1100 1011 110
181 ARM64_SYSREG_ICC_SGI0R_EL1 = 0xc65f, // 11 000 1100 1011 111
182} arm64_msr_reg;
183
184/// System PState Field (MSR instruction)
185typedef enum arm64_pstate {
186 ARM64_PSTATE_INVALID = 0,
187 ARM64_PSTATE_SPSEL = 0x05,
188 ARM64_PSTATE_DAIFSET = 0x1e,
189 ARM64_PSTATE_DAIFCLR = 0x1f
190} arm64_pstate;
191
192/// Vector arrangement specifier (for FloatingPoint/Advanced SIMD insn)
193typedef enum arm64_vas {
194 ARM64_VAS_INVALID = 0,
195 ARM64_VAS_8B,
196 ARM64_VAS_16B,
197 ARM64_VAS_4H,
198 ARM64_VAS_8H,
199 ARM64_VAS_2S,
200 ARM64_VAS_4S,
201 ARM64_VAS_1D,
202 ARM64_VAS_2D,
203 ARM64_VAS_1Q,
204} arm64_vas;
205
206/// Vector element size specifier
207typedef enum arm64_vess {
208 ARM64_VESS_INVALID = 0,
209 ARM64_VESS_B,
210 ARM64_VESS_H,
211 ARM64_VESS_S,
212 ARM64_VESS_D,
213} arm64_vess;
214
215/// Memory barrier operands
216typedef enum arm64_barrier_op {
217 ARM64_BARRIER_INVALID = 0,
218 ARM64_BARRIER_OSHLD = 0x1,
219 ARM64_BARRIER_OSHST = 0x2,
220 ARM64_BARRIER_OSH = 0x3,
221 ARM64_BARRIER_NSHLD = 0x5,
222 ARM64_BARRIER_NSHST = 0x6,
223 ARM64_BARRIER_NSH = 0x7,
224 ARM64_BARRIER_ISHLD = 0x9,
225 ARM64_BARRIER_ISHST = 0xa,
226 ARM64_BARRIER_ISH = 0xb,
227 ARM64_BARRIER_LD = 0xd,
228 ARM64_BARRIER_ST = 0xe,
229 ARM64_BARRIER_SY = 0xf
230} arm64_barrier_op;
231
232/// Operand type for instruction's operands
233typedef enum arm64_op_type {
234 ARM64_OP_INVALID = 0, ///< = CS_OP_INVALID (Uninitialized).
235 ARM64_OP_REG, ///< = CS_OP_REG (Register operand).
236 ARM64_OP_IMM, ///< = CS_OP_IMM (Immediate operand).
237 ARM64_OP_MEM, ///< = CS_OP_MEM (Memory operand).
238 ARM64_OP_FP, ///< = CS_OP_FP (Floating-Point operand).
239 ARM64_OP_CIMM = 64, ///< C-Immediate
240 ARM64_OP_REG_MRS, ///< MRS register operand.
241 ARM64_OP_REG_MSR, ///< MSR register operand.
242 ARM64_OP_PSTATE, ///< PState operand.
243 ARM64_OP_SYS, ///< SYS operand for IC/DC/AT/TLBI instructions.
244 ARM64_OP_PREFETCH, ///< Prefetch operand (PRFM).
245 ARM64_OP_BARRIER, ///< Memory barrier operand (ISB/DMB/DSB instructions).
246} arm64_op_type;
247
248/// TLBI operations
249typedef enum arm64_tlbi_op {
250 ARM64_TLBI_INVALID = 0,
251 ARM64_TLBI_VMALLE1IS,
252 ARM64_TLBI_VAE1IS,
253 ARM64_TLBI_ASIDE1IS,
254 ARM64_TLBI_VAAE1IS,
255 ARM64_TLBI_VALE1IS,
256 ARM64_TLBI_VAALE1IS,
257 ARM64_TLBI_ALLE2IS,
258 ARM64_TLBI_VAE2IS,
259 ARM64_TLBI_ALLE1IS,
260 ARM64_TLBI_VALE2IS,
261 ARM64_TLBI_VMALLS12E1IS,
262 ARM64_TLBI_ALLE3IS,
263 ARM64_TLBI_VAE3IS,
264 ARM64_TLBI_VALE3IS,
265 ARM64_TLBI_IPAS2E1IS,
266 ARM64_TLBI_IPAS2LE1IS,
267 ARM64_TLBI_IPAS2E1,
268 ARM64_TLBI_IPAS2LE1,
269 ARM64_TLBI_VMALLE1,
270 ARM64_TLBI_VAE1,
271 ARM64_TLBI_ASIDE1,
272 ARM64_TLBI_VAAE1,
273 ARM64_TLBI_VALE1,
274 ARM64_TLBI_VAALE1,
275 ARM64_TLBI_ALLE2,
276 ARM64_TLBI_VAE2,
277 ARM64_TLBI_ALLE1,
278 ARM64_TLBI_VALE2,
279 ARM64_TLBI_VMALLS12E1,
280 ARM64_TLBI_ALLE3,
281 ARM64_TLBI_VAE3,
282 ARM64_TLBI_VALE3,
283} arm64_tlbi_op;
284
285/// AT operations
286typedef enum arm64_at_op {
287 ARM64_AT_S1E1R,
288 ARM64_AT_S1E1W,
289 ARM64_AT_S1E0R,
290 ARM64_AT_S1E0W,
291 ARM64_AT_S1E2R,
292 ARM64_AT_S1E2W,
293 ARM64_AT_S12E1R,
294 ARM64_AT_S12E1W,
295 ARM64_AT_S12E0R,
296 ARM64_AT_S12E0W,
297 ARM64_AT_S1E3R,
298 ARM64_AT_S1E3W,
299} arm64_at_op;
300
301/// DC operations
302typedef enum arm64_dc_op {
303 ARM64_DC_INVALID = 0,
304 ARM64_DC_ZVA,
305 ARM64_DC_IVAC,
306 ARM64_DC_ISW,
307 ARM64_DC_CVAC,
308 ARM64_DC_CSW,
309 ARM64_DC_CVAU,
310 ARM64_DC_CIVAC,
311 ARM64_DC_CISW,
312} arm64_dc_op;
313
314/// IC operations
315typedef enum arm64_ic_op {
316 ARM64_IC_INVALID = 0,
317 ARM64_IC_IALLUIS,
318 ARM64_IC_IALLU,
319 ARM64_IC_IVAU,
320} arm64_ic_op;
321
322/// Prefetch operations (PRFM)
323typedef enum arm64_prefetch_op {
324 ARM64_PRFM_INVALID = 0,
325 ARM64_PRFM_PLDL1KEEP = 0x00 + 1,
326 ARM64_PRFM_PLDL1STRM = 0x01 + 1,
327 ARM64_PRFM_PLDL2KEEP = 0x02 + 1,
328 ARM64_PRFM_PLDL2STRM = 0x03 + 1,
329 ARM64_PRFM_PLDL3KEEP = 0x04 + 1,
330 ARM64_PRFM_PLDL3STRM = 0x05 + 1,
331 ARM64_PRFM_PLIL1KEEP = 0x08 + 1,
332 ARM64_PRFM_PLIL1STRM = 0x09 + 1,
333 ARM64_PRFM_PLIL2KEEP = 0x0a + 1,
334 ARM64_PRFM_PLIL2STRM = 0x0b + 1,
335 ARM64_PRFM_PLIL3KEEP = 0x0c + 1,
336 ARM64_PRFM_PLIL3STRM = 0x0d + 1,
337 ARM64_PRFM_PSTL1KEEP = 0x10 + 1,
338 ARM64_PRFM_PSTL1STRM = 0x11 + 1,
339 ARM64_PRFM_PSTL2KEEP = 0x12 + 1,
340 ARM64_PRFM_PSTL2STRM = 0x13 + 1,
341 ARM64_PRFM_PSTL3KEEP = 0x14 + 1,
342 ARM64_PRFM_PSTL3STRM = 0x15 + 1,
343} arm64_prefetch_op;
344
345
346/// ARM64 registers
347typedef enum arm64_reg {
348 ARM64_REG_INVALID = 0,
349
350 ARM64_REG_X29,
351 ARM64_REG_X30,
352 ARM64_REG_NZCV,
353 ARM64_REG_SP,
354 ARM64_REG_WSP,
355 ARM64_REG_WZR,
356 ARM64_REG_XZR,
357 ARM64_REG_B0,
358 ARM64_REG_B1,
359 ARM64_REG_B2,
360 ARM64_REG_B3,
361 ARM64_REG_B4,
362 ARM64_REG_B5,
363 ARM64_REG_B6,
364 ARM64_REG_B7,
365 ARM64_REG_B8,
366 ARM64_REG_B9,
367 ARM64_REG_B10,
368 ARM64_REG_B11,
369 ARM64_REG_B12,
370 ARM64_REG_B13,
371 ARM64_REG_B14,
372 ARM64_REG_B15,
373 ARM64_REG_B16,
374 ARM64_REG_B17,
375 ARM64_REG_B18,
376 ARM64_REG_B19,
377 ARM64_REG_B20,
378 ARM64_REG_B21,
379 ARM64_REG_B22,
380 ARM64_REG_B23,
381 ARM64_REG_B24,
382 ARM64_REG_B25,
383 ARM64_REG_B26,
384 ARM64_REG_B27,
385 ARM64_REG_B28,
386 ARM64_REG_B29,
387 ARM64_REG_B30,
388 ARM64_REG_B31,
389 ARM64_REG_D0,
390 ARM64_REG_D1,
391 ARM64_REG_D2,
392 ARM64_REG_D3,
393 ARM64_REG_D4,
394 ARM64_REG_D5,
395 ARM64_REG_D6,
396 ARM64_REG_D7,
397 ARM64_REG_D8,
398 ARM64_REG_D9,
399 ARM64_REG_D10,
400 ARM64_REG_D11,
401 ARM64_REG_D12,
402 ARM64_REG_D13,
403 ARM64_REG_D14,
404 ARM64_REG_D15,
405 ARM64_REG_D16,
406 ARM64_REG_D17,
407 ARM64_REG_D18,
408 ARM64_REG_D19,
409 ARM64_REG_D20,
410 ARM64_REG_D21,
411 ARM64_REG_D22,
412 ARM64_REG_D23,
413 ARM64_REG_D24,
414 ARM64_REG_D25,
415 ARM64_REG_D26,
416 ARM64_REG_D27,
417 ARM64_REG_D28,
418 ARM64_REG_D29,
419 ARM64_REG_D30,
420 ARM64_REG_D31,
421 ARM64_REG_H0,
422 ARM64_REG_H1,
423 ARM64_REG_H2,
424 ARM64_REG_H3,
425 ARM64_REG_H4,
426 ARM64_REG_H5,
427 ARM64_REG_H6,
428 ARM64_REG_H7,
429 ARM64_REG_H8,
430 ARM64_REG_H9,
431 ARM64_REG_H10,
432 ARM64_REG_H11,
433 ARM64_REG_H12,
434 ARM64_REG_H13,
435 ARM64_REG_H14,
436 ARM64_REG_H15,
437 ARM64_REG_H16,
438 ARM64_REG_H17,
439 ARM64_REG_H18,
440 ARM64_REG_H19,
441 ARM64_REG_H20,
442 ARM64_REG_H21,
443 ARM64_REG_H22,
444 ARM64_REG_H23,
445 ARM64_REG_H24,
446 ARM64_REG_H25,
447 ARM64_REG_H26,
448 ARM64_REG_H27,
449 ARM64_REG_H28,
450 ARM64_REG_H29,
451 ARM64_REG_H30,
452 ARM64_REG_H31,
453 ARM64_REG_Q0,
454 ARM64_REG_Q1,
455 ARM64_REG_Q2,
456 ARM64_REG_Q3,
457 ARM64_REG_Q4,
458 ARM64_REG_Q5,
459 ARM64_REG_Q6,
460 ARM64_REG_Q7,
461 ARM64_REG_Q8,
462 ARM64_REG_Q9,
463 ARM64_REG_Q10,
464 ARM64_REG_Q11,
465 ARM64_REG_Q12,
466 ARM64_REG_Q13,
467 ARM64_REG_Q14,
468 ARM64_REG_Q15,
469 ARM64_REG_Q16,
470 ARM64_REG_Q17,
471 ARM64_REG_Q18,
472 ARM64_REG_Q19,
473 ARM64_REG_Q20,
474 ARM64_REG_Q21,
475 ARM64_REG_Q22,
476 ARM64_REG_Q23,
477 ARM64_REG_Q24,
478 ARM64_REG_Q25,
479 ARM64_REG_Q26,
480 ARM64_REG_Q27,
481 ARM64_REG_Q28,
482 ARM64_REG_Q29,
483 ARM64_REG_Q30,
484 ARM64_REG_Q31,
485 ARM64_REG_S0,
486 ARM64_REG_S1,
487 ARM64_REG_S2,
488 ARM64_REG_S3,
489 ARM64_REG_S4,
490 ARM64_REG_S5,
491 ARM64_REG_S6,
492 ARM64_REG_S7,
493 ARM64_REG_S8,
494 ARM64_REG_S9,
495 ARM64_REG_S10,
496 ARM64_REG_S11,
497 ARM64_REG_S12,
498 ARM64_REG_S13,
499 ARM64_REG_S14,
500 ARM64_REG_S15,
501 ARM64_REG_S16,
502 ARM64_REG_S17,
503 ARM64_REG_S18,
504 ARM64_REG_S19,
505 ARM64_REG_S20,
506 ARM64_REG_S21,
507 ARM64_REG_S22,
508 ARM64_REG_S23,
509 ARM64_REG_S24,
510 ARM64_REG_S25,
511 ARM64_REG_S26,
512 ARM64_REG_S27,
513 ARM64_REG_S28,
514 ARM64_REG_S29,
515 ARM64_REG_S30,
516 ARM64_REG_S31,
517 ARM64_REG_W0,
518 ARM64_REG_W1,
519 ARM64_REG_W2,
520 ARM64_REG_W3,
521 ARM64_REG_W4,
522 ARM64_REG_W5,
523 ARM64_REG_W6,
524 ARM64_REG_W7,
525 ARM64_REG_W8,
526 ARM64_REG_W9,
527 ARM64_REG_W10,
528 ARM64_REG_W11,
529 ARM64_REG_W12,
530 ARM64_REG_W13,
531 ARM64_REG_W14,
532 ARM64_REG_W15,
533 ARM64_REG_W16,
534 ARM64_REG_W17,
535 ARM64_REG_W18,
536 ARM64_REG_W19,
537 ARM64_REG_W20,
538 ARM64_REG_W21,
539 ARM64_REG_W22,
540 ARM64_REG_W23,
541 ARM64_REG_W24,
542 ARM64_REG_W25,
543 ARM64_REG_W26,
544 ARM64_REG_W27,
545 ARM64_REG_W28,
546 ARM64_REG_W29,
547 ARM64_REG_W30,
548 ARM64_REG_X0,
549 ARM64_REG_X1,
550 ARM64_REG_X2,
551 ARM64_REG_X3,
552 ARM64_REG_X4,
553 ARM64_REG_X5,
554 ARM64_REG_X6,
555 ARM64_REG_X7,
556 ARM64_REG_X8,
557 ARM64_REG_X9,
558 ARM64_REG_X10,
559 ARM64_REG_X11,
560 ARM64_REG_X12,
561 ARM64_REG_X13,
562 ARM64_REG_X14,
563 ARM64_REG_X15,
564 ARM64_REG_X16,
565 ARM64_REG_X17,
566 ARM64_REG_X18,
567 ARM64_REG_X19,
568 ARM64_REG_X20,
569 ARM64_REG_X21,
570 ARM64_REG_X22,
571 ARM64_REG_X23,
572 ARM64_REG_X24,
573 ARM64_REG_X25,
574 ARM64_REG_X26,
575 ARM64_REG_X27,
576 ARM64_REG_X28,
577
578 ARM64_REG_V0,
579 ARM64_REG_V1,
580 ARM64_REG_V2,
581 ARM64_REG_V3,
582 ARM64_REG_V4,
583 ARM64_REG_V5,
584 ARM64_REG_V6,
585 ARM64_REG_V7,
586 ARM64_REG_V8,
587 ARM64_REG_V9,
588 ARM64_REG_V10,
589 ARM64_REG_V11,
590 ARM64_REG_V12,
591 ARM64_REG_V13,
592 ARM64_REG_V14,
593 ARM64_REG_V15,
594 ARM64_REG_V16,
595 ARM64_REG_V17,
596 ARM64_REG_V18,
597 ARM64_REG_V19,
598 ARM64_REG_V20,
599 ARM64_REG_V21,
600 ARM64_REG_V22,
601 ARM64_REG_V23,
602 ARM64_REG_V24,
603 ARM64_REG_V25,
604 ARM64_REG_V26,
605 ARM64_REG_V27,
606 ARM64_REG_V28,
607 ARM64_REG_V29,
608 ARM64_REG_V30,
609 ARM64_REG_V31,
610
611 ARM64_REG_ENDING, // <-- mark the end of the list of registers
612
613 // alias registers
614
615 ARM64_REG_IP0 = ARM64_REG_X16,
616 ARM64_REG_IP1 = ARM64_REG_X17,
617 ARM64_REG_FP = ARM64_REG_X29,
618 ARM64_REG_LR = ARM64_REG_X30,
619} arm64_reg;
620
621/// Instruction's operand referring to memory
622/// This is associated with ARM64_OP_MEM operand type above
623typedef struct arm64_op_mem {
624 arm64_reg base; ///< base register
625 arm64_reg index; ///< index register
626 int32_t disp; ///< displacement/offset value
627} arm64_op_mem;
628
629/// Instruction operand
630typedef struct cs_arm64_op {
631 int vector_index; ///< Vector Index for some vector operands (or -1 if irrelevant)
632 arm64_vas vas; ///< Vector Arrangement Specifier
633 arm64_vess vess; ///< Vector Element Size Specifier
634 struct {
635 arm64_shifter type; ///< shifter type of this operand
636 unsigned int value; ///< shifter value of this operand
637 } shift;
638 arm64_extender ext; ///< extender type of this operand
639 arm64_op_type type; ///< operand type
640 union {
641 arm64_reg reg; ///< register value for REG operand
642 int64_t imm; ///< immediate value, or index for C-IMM or IMM operand
643 double fp; ///< floating point value for FP operand
644 arm64_op_mem mem; ///< base/index/scale/disp value for MEM operand
645 arm64_pstate pstate; ///< PState field of MSR instruction.
646 unsigned int sys; ///< IC/DC/AT/TLBI operation (see arm64_ic_op, arm64_dc_op, arm64_at_op, arm64_tlbi_op)
647 arm64_prefetch_op prefetch; ///< PRFM operation.
648 arm64_barrier_op barrier; ///< Memory barrier operation (ISB/DMB/DSB instructions).
649 };
650
651 /// How is this operand accessed? (READ, WRITE or READ|WRITE)
652 /// This field is combined of cs_ac_type.
653 /// NOTE: this field is irrelevant if engine is compiled in DIET mode.
654 uint8_t access;
655} cs_arm64_op;
656
657/// Instruction structure
658typedef struct cs_arm64 {
659 arm64_cc cc; ///< conditional code for this insn
660 bool update_flags; ///< does this insn update flags?
661 bool writeback; ///< does this insn request writeback? 'True' means 'yes'
662
663 /// Number of operands of this instruction,
664 /// or 0 when instruction has no operand.
665 uint8_t op_count;
666
667 cs_arm64_op operands[8]; ///< operands for this instruction.
668} cs_arm64;
669
670/// ARM64 instruction
671typedef enum arm64_insn {
672 ARM64_INS_INVALID = 0,
673
674 ARM64_INS_ABS,
675 ARM64_INS_ADC,
676 ARM64_INS_ADDHN,
677 ARM64_INS_ADDHN2,
678 ARM64_INS_ADDP,
679 ARM64_INS_ADD,
680 ARM64_INS_ADDV,
681 ARM64_INS_ADR,
682 ARM64_INS_ADRP,
683 ARM64_INS_AESD,
684 ARM64_INS_AESE,
685 ARM64_INS_AESIMC,
686 ARM64_INS_AESMC,
687 ARM64_INS_AND,
688 ARM64_INS_ASR,
689 ARM64_INS_B,
690 ARM64_INS_BFM,
691 ARM64_INS_BIC,
692 ARM64_INS_BIF,
693 ARM64_INS_BIT,
694 ARM64_INS_BL,
695 ARM64_INS_BLR,
696 ARM64_INS_BR,
697 ARM64_INS_BRK,
698 ARM64_INS_BSL,
699 ARM64_INS_CBNZ,
700 ARM64_INS_CBZ,
701 ARM64_INS_CCMN,
702 ARM64_INS_CCMP,
703 ARM64_INS_CLREX,
704 ARM64_INS_CLS,
705 ARM64_INS_CLZ,
706 ARM64_INS_CMEQ,
707 ARM64_INS_CMGE,
708 ARM64_INS_CMGT,
709 ARM64_INS_CMHI,
710 ARM64_INS_CMHS,
711 ARM64_INS_CMLE,
712 ARM64_INS_CMLT,
713 ARM64_INS_CMTST,
714 ARM64_INS_CNT,
715 ARM64_INS_MOV,
716 ARM64_INS_CRC32B,
717 ARM64_INS_CRC32CB,
718 ARM64_INS_CRC32CH,
719 ARM64_INS_CRC32CW,
720 ARM64_INS_CRC32CX,
721 ARM64_INS_CRC32H,
722 ARM64_INS_CRC32W,
723 ARM64_INS_CRC32X,
724 ARM64_INS_CSEL,
725 ARM64_INS_CSINC,
726 ARM64_INS_CSINV,
727 ARM64_INS_CSNEG,
728 ARM64_INS_DCPS1,
729 ARM64_INS_DCPS2,
730 ARM64_INS_DCPS3,
731 ARM64_INS_DMB,
732 ARM64_INS_DRPS,
733 ARM64_INS_DSB,
734 ARM64_INS_DUP,
735 ARM64_INS_EON,
736 ARM64_INS_EOR,
737 ARM64_INS_ERET,
738 ARM64_INS_EXTR,
739 ARM64_INS_EXT,
740 ARM64_INS_FABD,
741 ARM64_INS_FABS,
742 ARM64_INS_FACGE,
743 ARM64_INS_FACGT,
744 ARM64_INS_FADD,
745 ARM64_INS_FADDP,
746 ARM64_INS_FCCMP,
747 ARM64_INS_FCCMPE,
748 ARM64_INS_FCMEQ,
749 ARM64_INS_FCMGE,
750 ARM64_INS_FCMGT,
751 ARM64_INS_FCMLE,
752 ARM64_INS_FCMLT,
753 ARM64_INS_FCMP,
754 ARM64_INS_FCMPE,
755 ARM64_INS_FCSEL,
756 ARM64_INS_FCVTAS,
757 ARM64_INS_FCVTAU,
758 ARM64_INS_FCVT,
759 ARM64_INS_FCVTL,
760 ARM64_INS_FCVTL2,
761 ARM64_INS_FCVTMS,
762 ARM64_INS_FCVTMU,
763 ARM64_INS_FCVTNS,
764 ARM64_INS_FCVTNU,
765 ARM64_INS_FCVTN,
766 ARM64_INS_FCVTN2,
767 ARM64_INS_FCVTPS,
768 ARM64_INS_FCVTPU,
769 ARM64_INS_FCVTXN,
770 ARM64_INS_FCVTXN2,
771 ARM64_INS_FCVTZS,
772 ARM64_INS_FCVTZU,
773 ARM64_INS_FDIV,
774 ARM64_INS_FMADD,
775 ARM64_INS_FMAX,
776 ARM64_INS_FMAXNM,
777 ARM64_INS_FMAXNMP,
778 ARM64_INS_FMAXNMV,
779 ARM64_INS_FMAXP,
780 ARM64_INS_FMAXV,
781 ARM64_INS_FMIN,
782 ARM64_INS_FMINNM,
783 ARM64_INS_FMINNMP,
784 ARM64_INS_FMINNMV,
785 ARM64_INS_FMINP,
786 ARM64_INS_FMINV,
787 ARM64_INS_FMLA,
788 ARM64_INS_FMLS,
789 ARM64_INS_FMOV,
790 ARM64_INS_FMSUB,
791 ARM64_INS_FMUL,
792 ARM64_INS_FMULX,
793 ARM64_INS_FNEG,
794 ARM64_INS_FNMADD,
795 ARM64_INS_FNMSUB,
796 ARM64_INS_FNMUL,
797 ARM64_INS_FRECPE,
798 ARM64_INS_FRECPS,
799 ARM64_INS_FRECPX,
800 ARM64_INS_FRINTA,
801 ARM64_INS_FRINTI,
802 ARM64_INS_FRINTM,
803 ARM64_INS_FRINTN,
804 ARM64_INS_FRINTP,
805 ARM64_INS_FRINTX,
806 ARM64_INS_FRINTZ,
807 ARM64_INS_FRSQRTE,
808 ARM64_INS_FRSQRTS,
809 ARM64_INS_FSQRT,
810 ARM64_INS_FSUB,
811 ARM64_INS_HINT,
812 ARM64_INS_HLT,
813 ARM64_INS_HVC,
814 ARM64_INS_INS,
815
816 ARM64_INS_ISB,
817 ARM64_INS_LD1,
818 ARM64_INS_LD1R,
819 ARM64_INS_LD2R,
820 ARM64_INS_LD2,
821 ARM64_INS_LD3R,
822 ARM64_INS_LD3,
823 ARM64_INS_LD4,
824 ARM64_INS_LD4R,
825
826 ARM64_INS_LDARB,
827 ARM64_INS_LDARH,
828 ARM64_INS_LDAR,
829 ARM64_INS_LDAXP,
830 ARM64_INS_LDAXRB,
831 ARM64_INS_LDAXRH,
832 ARM64_INS_LDAXR,
833 ARM64_INS_LDNP,
834 ARM64_INS_LDP,
835 ARM64_INS_LDPSW,
836 ARM64_INS_LDRB,
837 ARM64_INS_LDR,
838 ARM64_INS_LDRH,
839 ARM64_INS_LDRSB,
840 ARM64_INS_LDRSH,
841 ARM64_INS_LDRSW,
842 ARM64_INS_LDTRB,
843 ARM64_INS_LDTRH,
844 ARM64_INS_LDTRSB,
845
846 ARM64_INS_LDTRSH,
847 ARM64_INS_LDTRSW,
848 ARM64_INS_LDTR,
849 ARM64_INS_LDURB,
850 ARM64_INS_LDUR,
851 ARM64_INS_LDURH,
852 ARM64_INS_LDURSB,
853 ARM64_INS_LDURSH,
854 ARM64_INS_LDURSW,
855 ARM64_INS_LDXP,
856 ARM64_INS_LDXRB,
857 ARM64_INS_LDXRH,
858 ARM64_INS_LDXR,
859 ARM64_INS_LSL,
860 ARM64_INS_LSR,
861 ARM64_INS_MADD,
862 ARM64_INS_MLA,
863 ARM64_INS_MLS,
864 ARM64_INS_MOVI,
865 ARM64_INS_MOVK,
866 ARM64_INS_MOVN,
867 ARM64_INS_MOVZ,
868 ARM64_INS_MRS,
869 ARM64_INS_MSR,
870 ARM64_INS_MSUB,
871 ARM64_INS_MUL,
872 ARM64_INS_MVNI,
873 ARM64_INS_NEG,
874 ARM64_INS_NOT,
875 ARM64_INS_ORN,
876 ARM64_INS_ORR,
877 ARM64_INS_PMULL2,
878 ARM64_INS_PMULL,
879 ARM64_INS_PMUL,
880 ARM64_INS_PRFM,
881 ARM64_INS_PRFUM,
882 ARM64_INS_RADDHN,
883 ARM64_INS_RADDHN2,
884 ARM64_INS_RBIT,
885 ARM64_INS_RET,
886 ARM64_INS_REV16,
887 ARM64_INS_REV32,
888 ARM64_INS_REV64,
889 ARM64_INS_REV,
890 ARM64_INS_ROR,
891 ARM64_INS_RSHRN2,
892 ARM64_INS_RSHRN,
893 ARM64_INS_RSUBHN,
894 ARM64_INS_RSUBHN2,
895 ARM64_INS_SABAL2,
896 ARM64_INS_SABAL,
897
898 ARM64_INS_SABA,
899 ARM64_INS_SABDL2,
900 ARM64_INS_SABDL,
901 ARM64_INS_SABD,
902 ARM64_INS_SADALP,
903 ARM64_INS_SADDLP,
904 ARM64_INS_SADDLV,
905 ARM64_INS_SADDL2,
906 ARM64_INS_SADDL,
907 ARM64_INS_SADDW2,
908 ARM64_INS_SADDW,
909 ARM64_INS_SBC,
910 ARM64_INS_SBFM,
911 ARM64_INS_SCVTF,
912 ARM64_INS_SDIV,
913 ARM64_INS_SHA1C,
914 ARM64_INS_SHA1H,
915 ARM64_INS_SHA1M,
916 ARM64_INS_SHA1P,
917 ARM64_INS_SHA1SU0,
918 ARM64_INS_SHA1SU1,
919 ARM64_INS_SHA256H2,
920 ARM64_INS_SHA256H,
921 ARM64_INS_SHA256SU0,
922 ARM64_INS_SHA256SU1,
923 ARM64_INS_SHADD,
924 ARM64_INS_SHLL2,
925 ARM64_INS_SHLL,
926 ARM64_INS_SHL,
927 ARM64_INS_SHRN2,
928 ARM64_INS_SHRN,
929 ARM64_INS_SHSUB,
930 ARM64_INS_SLI,
931 ARM64_INS_SMADDL,
932 ARM64_INS_SMAXP,
933 ARM64_INS_SMAXV,
934 ARM64_INS_SMAX,
935 ARM64_INS_SMC,
936 ARM64_INS_SMINP,
937 ARM64_INS_SMINV,
938 ARM64_INS_SMIN,
939 ARM64_INS_SMLAL2,
940 ARM64_INS_SMLAL,
941 ARM64_INS_SMLSL2,
942 ARM64_INS_SMLSL,
943 ARM64_INS_SMOV,
944 ARM64_INS_SMSUBL,
945 ARM64_INS_SMULH,
946 ARM64_INS_SMULL2,
947 ARM64_INS_SMULL,
948 ARM64_INS_SQABS,
949 ARM64_INS_SQADD,
950 ARM64_INS_SQDMLAL,
951 ARM64_INS_SQDMLAL2,
952 ARM64_INS_SQDMLSL,
953 ARM64_INS_SQDMLSL2,
954 ARM64_INS_SQDMULH,
955 ARM64_INS_SQDMULL,
956 ARM64_INS_SQDMULL2,
957 ARM64_INS_SQNEG,
958 ARM64_INS_SQRDMULH,
959 ARM64_INS_SQRSHL,
960 ARM64_INS_SQRSHRN,
961 ARM64_INS_SQRSHRN2,
962 ARM64_INS_SQRSHRUN,
963 ARM64_INS_SQRSHRUN2,
964 ARM64_INS_SQSHLU,
965 ARM64_INS_SQSHL,
966 ARM64_INS_SQSHRN,
967 ARM64_INS_SQSHRN2,
968 ARM64_INS_SQSHRUN,
969 ARM64_INS_SQSHRUN2,
970 ARM64_INS_SQSUB,
971 ARM64_INS_SQXTN2,
972 ARM64_INS_SQXTN,
973 ARM64_INS_SQXTUN2,
974 ARM64_INS_SQXTUN,
975 ARM64_INS_SRHADD,
976 ARM64_INS_SRI,
977 ARM64_INS_SRSHL,
978 ARM64_INS_SRSHR,
979 ARM64_INS_SRSRA,
980 ARM64_INS_SSHLL2,
981 ARM64_INS_SSHLL,
982 ARM64_INS_SSHL,
983 ARM64_INS_SSHR,
984 ARM64_INS_SSRA,
985 ARM64_INS_SSUBL2,
986 ARM64_INS_SSUBL,
987 ARM64_INS_SSUBW2,
988 ARM64_INS_SSUBW,
989 ARM64_INS_ST1,
990 ARM64_INS_ST2,
991 ARM64_INS_ST3,
992 ARM64_INS_ST4,
993 ARM64_INS_STLRB,
994 ARM64_INS_STLRH,
995 ARM64_INS_STLR,
996 ARM64_INS_STLXP,
997 ARM64_INS_STLXRB,
998 ARM64_INS_STLXRH,
999 ARM64_INS_STLXR,
1000 ARM64_INS_STNP,
1001 ARM64_INS_STP,
1002 ARM64_INS_STRB,
1003 ARM64_INS_STR,
1004 ARM64_INS_STRH,
1005 ARM64_INS_STTRB,
1006 ARM64_INS_STTRH,
1007 ARM64_INS_STTR,
1008 ARM64_INS_STURB,
1009 ARM64_INS_STUR,
1010 ARM64_INS_STURH,
1011 ARM64_INS_STXP,
1012 ARM64_INS_STXRB,
1013 ARM64_INS_STXRH,
1014 ARM64_INS_STXR,
1015 ARM64_INS_SUBHN,
1016 ARM64_INS_SUBHN2,
1017 ARM64_INS_SUB,
1018 ARM64_INS_SUQADD,
1019 ARM64_INS_SVC,
1020 ARM64_INS_SYSL,
1021 ARM64_INS_SYS,
1022 ARM64_INS_TBL,
1023 ARM64_INS_TBNZ,
1024 ARM64_INS_TBX,
1025 ARM64_INS_TBZ,
1026 ARM64_INS_TRN1,
1027 ARM64_INS_TRN2,
1028 ARM64_INS_UABAL2,
1029 ARM64_INS_UABAL,
1030 ARM64_INS_UABA,
1031 ARM64_INS_UABDL2,
1032 ARM64_INS_UABDL,
1033 ARM64_INS_UABD,
1034 ARM64_INS_UADALP,
1035 ARM64_INS_UADDLP,
1036 ARM64_INS_UADDLV,
1037 ARM64_INS_UADDL2,
1038 ARM64_INS_UADDL,
1039 ARM64_INS_UADDW2,
1040 ARM64_INS_UADDW,
1041 ARM64_INS_UBFM,
1042 ARM64_INS_UCVTF,
1043 ARM64_INS_UDIV,
1044 ARM64_INS_UHADD,
1045 ARM64_INS_UHSUB,
1046 ARM64_INS_UMADDL,
1047 ARM64_INS_UMAXP,
1048 ARM64_INS_UMAXV,
1049 ARM64_INS_UMAX,
1050 ARM64_INS_UMINP,
1051 ARM64_INS_UMINV,
1052 ARM64_INS_UMIN,
1053 ARM64_INS_UMLAL2,
1054 ARM64_INS_UMLAL,
1055 ARM64_INS_UMLSL2,
1056 ARM64_INS_UMLSL,
1057 ARM64_INS_UMOV,
1058 ARM64_INS_UMSUBL,
1059 ARM64_INS_UMULH,
1060 ARM64_INS_UMULL2,
1061 ARM64_INS_UMULL,
1062 ARM64_INS_UQADD,
1063 ARM64_INS_UQRSHL,
1064 ARM64_INS_UQRSHRN,
1065 ARM64_INS_UQRSHRN2,
1066 ARM64_INS_UQSHL,
1067 ARM64_INS_UQSHRN,
1068 ARM64_INS_UQSHRN2,
1069 ARM64_INS_UQSUB,
1070 ARM64_INS_UQXTN2,
1071 ARM64_INS_UQXTN,
1072 ARM64_INS_URECPE,
1073 ARM64_INS_URHADD,
1074 ARM64_INS_URSHL,
1075 ARM64_INS_URSHR,
1076 ARM64_INS_URSQRTE,
1077 ARM64_INS_URSRA,
1078 ARM64_INS_USHLL2,
1079 ARM64_INS_USHLL,
1080 ARM64_INS_USHL,
1081 ARM64_INS_USHR,
1082 ARM64_INS_USQADD,
1083 ARM64_INS_USRA,
1084 ARM64_INS_USUBL2,
1085 ARM64_INS_USUBL,
1086 ARM64_INS_USUBW2,
1087 ARM64_INS_USUBW,
1088 ARM64_INS_UZP1,
1089 ARM64_INS_UZP2,
1090 ARM64_INS_XTN2,
1091 ARM64_INS_XTN,
1092 ARM64_INS_ZIP1,
1093 ARM64_INS_ZIP2,
1094
1095 // alias insn
1096 ARM64_INS_MNEG,
1097 ARM64_INS_UMNEGL,
1098 ARM64_INS_SMNEGL,
1099 ARM64_INS_NOP,
1100 ARM64_INS_YIELD,
1101 ARM64_INS_WFE,
1102 ARM64_INS_WFI,
1103 ARM64_INS_SEV,
1104 ARM64_INS_SEVL,
1105 ARM64_INS_NGC,
1106 ARM64_INS_SBFIZ,
1107 ARM64_INS_UBFIZ,
1108 ARM64_INS_SBFX,
1109 ARM64_INS_UBFX,
1110 ARM64_INS_BFI,
1111 ARM64_INS_BFXIL,
1112 ARM64_INS_CMN,
1113 ARM64_INS_MVN,
1114 ARM64_INS_TST,
1115 ARM64_INS_CSET,
1116 ARM64_INS_CINC,
1117 ARM64_INS_CSETM,
1118 ARM64_INS_CINV,
1119 ARM64_INS_CNEG,
1120 ARM64_INS_SXTB,
1121 ARM64_INS_SXTH,
1122 ARM64_INS_SXTW,
1123 ARM64_INS_CMP,
1124 ARM64_INS_UXTB,
1125 ARM64_INS_UXTH,
1126 ARM64_INS_UXTW,
1127 ARM64_INS_IC,
1128 ARM64_INS_DC,
1129 ARM64_INS_AT,
1130 ARM64_INS_TLBI,
1131
1132 ARM64_INS_NEGS,
1133 ARM64_INS_NGCS,
1134
1135 ARM64_INS_ENDING, // <-- mark the end of the list of insn
1136} arm64_insn;
1137
1138/// Group of ARM64 instructions
1139typedef enum arm64_insn_group {
1140 ARM64_GRP_INVALID = 0, ///< = CS_GRP_INVALID
1141
1142 // Generic groups
1143 // all jump instructions (conditional+direct+indirect jumps)
1144 ARM64_GRP_JUMP, ///< = CS_GRP_JUMP
1145 ARM64_GRP_CALL,
1146 ARM64_GRP_RET,
1147 ARM64_GRP_INT,
1148 ARM64_GRP_PRIVILEGE = 6, ///< = CS_GRP_PRIVILEGE
1149 ARM64_GRP_BRANCH_RELATIVE, ///< = CS_GRP_BRANCH_RELATIVE
1150
1151 // Architecture-specific groups
1152 ARM64_GRP_CRYPTO = 128,
1153 ARM64_GRP_FPARMV8,
1154 ARM64_GRP_NEON,
1155 ARM64_GRP_CRC,
1156
1157 ARM64_GRP_ENDING, // <-- mark the end of the list of groups
1158} arm64_insn_group;
1159
1160#ifdef __cplusplus
1161}
1162#endif
1163
1164#endif
1165