1/**************************************************************************/
2/* rendering_device.h */
3/**************************************************************************/
4/* This file is part of: */
5/* GODOT ENGINE */
6/* https://godotengine.org */
7/**************************************************************************/
8/* Copyright (c) 2014-present Godot Engine contributors (see AUTHORS.md). */
9/* Copyright (c) 2007-2014 Juan Linietsky, Ariel Manzur. */
10/* */
11/* Permission is hereby granted, free of charge, to any person obtaining */
12/* a copy of this software and associated documentation files (the */
13/* "Software"), to deal in the Software without restriction, including */
14/* without limitation the rights to use, copy, modify, merge, publish, */
15/* distribute, sublicense, and/or sell copies of the Software, and to */
16/* permit persons to whom the Software is furnished to do so, subject to */
17/* the following conditions: */
18/* */
19/* The above copyright notice and this permission notice shall be */
20/* included in all copies or substantial portions of the Software. */
21/* */
22/* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, */
23/* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF */
24/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. */
25/* IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY */
26/* CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, */
27/* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE */
28/* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. */
29/**************************************************************************/
30
31#ifndef RENDERING_DEVICE_H
32#define RENDERING_DEVICE_H
33
34#include "core/object/class_db.h"
35#include "core/variant/typed_array.h"
36#include "servers/display_server.h"
37
38class RDTextureFormat;
39class RDTextureView;
40class RDAttachmentFormat;
41class RDSamplerState;
42class RDVertexAttribute;
43class RDShaderSource;
44class RDShaderSPIRV;
45class RDUniform;
46class RDPipelineRasterizationState;
47class RDPipelineMultisampleState;
48class RDPipelineDepthStencilState;
49class RDPipelineColorBlendState;
50class RDFramebufferPass;
51class RDPipelineSpecializationConstant;
52
53class RenderingDevice : public Object {
54 GDCLASS(RenderingDevice, Object)
55public:
56 enum DeviceFamily {
57 DEVICE_UNKNOWN,
58 DEVICE_OPENGL,
59 DEVICE_VULKAN,
60 DEVICE_DIRECTX
61 };
62
63 // This enum matches VkPhysicalDeviceType (except for `DEVICE_TYPE_MAX`).
64 // Unlike VkPhysicalDeviceType, DeviceType is exposed to the scripting API.
65 enum DeviceType {
66 DEVICE_TYPE_OTHER,
67 DEVICE_TYPE_INTEGRATED_GPU,
68 DEVICE_TYPE_DISCRETE_GPU,
69 DEVICE_TYPE_VIRTUAL_GPU,
70 DEVICE_TYPE_CPU,
71 DEVICE_TYPE_MAX,
72 };
73
74 enum DriverResource {
75 DRIVER_RESOURCE_VULKAN_DEVICE = 0,
76 DRIVER_RESOURCE_VULKAN_PHYSICAL_DEVICE,
77 DRIVER_RESOURCE_VULKAN_INSTANCE,
78 DRIVER_RESOURCE_VULKAN_QUEUE,
79 DRIVER_RESOURCE_VULKAN_QUEUE_FAMILY_INDEX,
80 DRIVER_RESOURCE_VULKAN_IMAGE,
81 DRIVER_RESOURCE_VULKAN_IMAGE_VIEW,
82 DRIVER_RESOURCE_VULKAN_IMAGE_NATIVE_TEXTURE_FORMAT,
83 DRIVER_RESOURCE_VULKAN_SAMPLER,
84 DRIVER_RESOURCE_VULKAN_DESCRIPTOR_SET,
85 DRIVER_RESOURCE_VULKAN_BUFFER,
86 DRIVER_RESOURCE_VULKAN_COMPUTE_PIPELINE,
87 DRIVER_RESOURCE_VULKAN_RENDER_PIPELINE,
88 //next driver continue enum from 1000 to keep order
89 };
90
91 enum ShaderStage {
92 SHADER_STAGE_VERTEX,
93 SHADER_STAGE_FRAGMENT,
94 SHADER_STAGE_TESSELATION_CONTROL,
95 SHADER_STAGE_TESSELATION_EVALUATION,
96 SHADER_STAGE_COMPUTE,
97 SHADER_STAGE_MAX,
98 SHADER_STAGE_VERTEX_BIT = (1 << SHADER_STAGE_VERTEX),
99 SHADER_STAGE_FRAGMENT_BIT = (1 << SHADER_STAGE_FRAGMENT),
100 SHADER_STAGE_TESSELATION_CONTROL_BIT = (1 << SHADER_STAGE_TESSELATION_CONTROL),
101 SHADER_STAGE_TESSELATION_EVALUATION_BIT = (1 << SHADER_STAGE_TESSELATION_EVALUATION),
102 SHADER_STAGE_COMPUTE_BIT = (1 << SHADER_STAGE_COMPUTE),
103 };
104
105 enum ShaderLanguage {
106 SHADER_LANGUAGE_GLSL,
107 SHADER_LANGUAGE_HLSL
108 };
109
110 enum SubgroupOperations {
111 SUBGROUP_BASIC_BIT = 1,
112 SUBGROUP_VOTE_BIT = 2,
113 SUBGROUP_ARITHMETIC_BIT = 4,
114 SUBGROUP_BALLOT_BIT = 8,
115 SUBGROUP_SHUFFLE_BIT = 16,
116 SUBGROUP_SHUFFLE_RELATIVE_BIT = 32,
117 SUBGROUP_CLUSTERED_BIT = 64,
118 SUBGROUP_QUAD_BIT = 128,
119 };
120
121 struct Capabilities {
122 // main device info
123 DeviceFamily device_family = DEVICE_UNKNOWN;
124 uint32_t version_major = 1.0;
125 uint32_t version_minor = 0.0;
126 };
127
128 typedef String (*ShaderSPIRVGetCacheKeyFunction)(const RenderingDevice *p_render_device);
129 typedef Vector<uint8_t> (*ShaderCompileToSPIRVFunction)(ShaderStage p_stage, const String &p_source_code, ShaderLanguage p_language, String *r_error, const RenderingDevice *p_render_device);
130 typedef Vector<uint8_t> (*ShaderCacheFunction)(ShaderStage p_stage, const String &p_source_code, ShaderLanguage p_language);
131
132 typedef void (*InvalidationCallback)(void *);
133
134private:
135 static ShaderCompileToSPIRVFunction compile_to_spirv_function;
136 static ShaderCacheFunction cache_function;
137 static ShaderSPIRVGetCacheKeyFunction get_spirv_cache_key_function;
138
139 static RenderingDevice *singleton;
140
141protected:
142 static void _bind_methods();
143
144#ifndef DISABLE_DEPRECATED
145 RID _shader_create_from_bytecode_bind_compat_79606(const Vector<uint8_t> &p_shader_binary);
146 static void _bind_compatibility_methods();
147#endif
148
149 Capabilities device_capabilities;
150
151public:
152 //base numeric ID for all types
153 enum {
154 INVALID_ID = -1,
155 INVALID_FORMAT_ID = -1
156 };
157
158 /*****************/
159 /**** GENERIC ****/
160 /*****************/
161
162 enum CompareOperator {
163 COMPARE_OP_NEVER,
164 COMPARE_OP_LESS,
165 COMPARE_OP_EQUAL,
166 COMPARE_OP_LESS_OR_EQUAL,
167 COMPARE_OP_GREATER,
168 COMPARE_OP_NOT_EQUAL,
169 COMPARE_OP_GREATER_OR_EQUAL,
170 COMPARE_OP_ALWAYS,
171 COMPARE_OP_MAX //not an actual operator, just the amount of operators :D
172 };
173
174 enum DataFormat {
175 DATA_FORMAT_R4G4_UNORM_PACK8,
176 DATA_FORMAT_R4G4B4A4_UNORM_PACK16,
177 DATA_FORMAT_B4G4R4A4_UNORM_PACK16,
178 DATA_FORMAT_R5G6B5_UNORM_PACK16,
179 DATA_FORMAT_B5G6R5_UNORM_PACK16,
180 DATA_FORMAT_R5G5B5A1_UNORM_PACK16,
181 DATA_FORMAT_B5G5R5A1_UNORM_PACK16,
182 DATA_FORMAT_A1R5G5B5_UNORM_PACK16,
183 DATA_FORMAT_R8_UNORM,
184 DATA_FORMAT_R8_SNORM,
185 DATA_FORMAT_R8_USCALED,
186 DATA_FORMAT_R8_SSCALED,
187 DATA_FORMAT_R8_UINT,
188 DATA_FORMAT_R8_SINT,
189 DATA_FORMAT_R8_SRGB,
190 DATA_FORMAT_R8G8_UNORM,
191 DATA_FORMAT_R8G8_SNORM,
192 DATA_FORMAT_R8G8_USCALED,
193 DATA_FORMAT_R8G8_SSCALED,
194 DATA_FORMAT_R8G8_UINT,
195 DATA_FORMAT_R8G8_SINT,
196 DATA_FORMAT_R8G8_SRGB,
197 DATA_FORMAT_R8G8B8_UNORM,
198 DATA_FORMAT_R8G8B8_SNORM,
199 DATA_FORMAT_R8G8B8_USCALED,
200 DATA_FORMAT_R8G8B8_SSCALED,
201 DATA_FORMAT_R8G8B8_UINT,
202 DATA_FORMAT_R8G8B8_SINT,
203 DATA_FORMAT_R8G8B8_SRGB,
204 DATA_FORMAT_B8G8R8_UNORM,
205 DATA_FORMAT_B8G8R8_SNORM,
206 DATA_FORMAT_B8G8R8_USCALED,
207 DATA_FORMAT_B8G8R8_SSCALED,
208 DATA_FORMAT_B8G8R8_UINT,
209 DATA_FORMAT_B8G8R8_SINT,
210 DATA_FORMAT_B8G8R8_SRGB,
211 DATA_FORMAT_R8G8B8A8_UNORM,
212 DATA_FORMAT_R8G8B8A8_SNORM,
213 DATA_FORMAT_R8G8B8A8_USCALED,
214 DATA_FORMAT_R8G8B8A8_SSCALED,
215 DATA_FORMAT_R8G8B8A8_UINT,
216 DATA_FORMAT_R8G8B8A8_SINT,
217 DATA_FORMAT_R8G8B8A8_SRGB,
218 DATA_FORMAT_B8G8R8A8_UNORM,
219 DATA_FORMAT_B8G8R8A8_SNORM,
220 DATA_FORMAT_B8G8R8A8_USCALED,
221 DATA_FORMAT_B8G8R8A8_SSCALED,
222 DATA_FORMAT_B8G8R8A8_UINT,
223 DATA_FORMAT_B8G8R8A8_SINT,
224 DATA_FORMAT_B8G8R8A8_SRGB,
225 DATA_FORMAT_A8B8G8R8_UNORM_PACK32,
226 DATA_FORMAT_A8B8G8R8_SNORM_PACK32,
227 DATA_FORMAT_A8B8G8R8_USCALED_PACK32,
228 DATA_FORMAT_A8B8G8R8_SSCALED_PACK32,
229 DATA_FORMAT_A8B8G8R8_UINT_PACK32,
230 DATA_FORMAT_A8B8G8R8_SINT_PACK32,
231 DATA_FORMAT_A8B8G8R8_SRGB_PACK32,
232 DATA_FORMAT_A2R10G10B10_UNORM_PACK32,
233 DATA_FORMAT_A2R10G10B10_SNORM_PACK32,
234 DATA_FORMAT_A2R10G10B10_USCALED_PACK32,
235 DATA_FORMAT_A2R10G10B10_SSCALED_PACK32,
236 DATA_FORMAT_A2R10G10B10_UINT_PACK32,
237 DATA_FORMAT_A2R10G10B10_SINT_PACK32,
238 DATA_FORMAT_A2B10G10R10_UNORM_PACK32,
239 DATA_FORMAT_A2B10G10R10_SNORM_PACK32,
240 DATA_FORMAT_A2B10G10R10_USCALED_PACK32,
241 DATA_FORMAT_A2B10G10R10_SSCALED_PACK32,
242 DATA_FORMAT_A2B10G10R10_UINT_PACK32,
243 DATA_FORMAT_A2B10G10R10_SINT_PACK32,
244 DATA_FORMAT_R16_UNORM,
245 DATA_FORMAT_R16_SNORM,
246 DATA_FORMAT_R16_USCALED,
247 DATA_FORMAT_R16_SSCALED,
248 DATA_FORMAT_R16_UINT,
249 DATA_FORMAT_R16_SINT,
250 DATA_FORMAT_R16_SFLOAT,
251 DATA_FORMAT_R16G16_UNORM,
252 DATA_FORMAT_R16G16_SNORM,
253 DATA_FORMAT_R16G16_USCALED,
254 DATA_FORMAT_R16G16_SSCALED,
255 DATA_FORMAT_R16G16_UINT,
256 DATA_FORMAT_R16G16_SINT,
257 DATA_FORMAT_R16G16_SFLOAT,
258 DATA_FORMAT_R16G16B16_UNORM,
259 DATA_FORMAT_R16G16B16_SNORM,
260 DATA_FORMAT_R16G16B16_USCALED,
261 DATA_FORMAT_R16G16B16_SSCALED,
262 DATA_FORMAT_R16G16B16_UINT,
263 DATA_FORMAT_R16G16B16_SINT,
264 DATA_FORMAT_R16G16B16_SFLOAT,
265 DATA_FORMAT_R16G16B16A16_UNORM,
266 DATA_FORMAT_R16G16B16A16_SNORM,
267 DATA_FORMAT_R16G16B16A16_USCALED,
268 DATA_FORMAT_R16G16B16A16_SSCALED,
269 DATA_FORMAT_R16G16B16A16_UINT,
270 DATA_FORMAT_R16G16B16A16_SINT,
271 DATA_FORMAT_R16G16B16A16_SFLOAT,
272 DATA_FORMAT_R32_UINT,
273 DATA_FORMAT_R32_SINT,
274 DATA_FORMAT_R32_SFLOAT,
275 DATA_FORMAT_R32G32_UINT,
276 DATA_FORMAT_R32G32_SINT,
277 DATA_FORMAT_R32G32_SFLOAT,
278 DATA_FORMAT_R32G32B32_UINT,
279 DATA_FORMAT_R32G32B32_SINT,
280 DATA_FORMAT_R32G32B32_SFLOAT,
281 DATA_FORMAT_R32G32B32A32_UINT,
282 DATA_FORMAT_R32G32B32A32_SINT,
283 DATA_FORMAT_R32G32B32A32_SFLOAT,
284 DATA_FORMAT_R64_UINT,
285 DATA_FORMAT_R64_SINT,
286 DATA_FORMAT_R64_SFLOAT,
287 DATA_FORMAT_R64G64_UINT,
288 DATA_FORMAT_R64G64_SINT,
289 DATA_FORMAT_R64G64_SFLOAT,
290 DATA_FORMAT_R64G64B64_UINT,
291 DATA_FORMAT_R64G64B64_SINT,
292 DATA_FORMAT_R64G64B64_SFLOAT,
293 DATA_FORMAT_R64G64B64A64_UINT,
294 DATA_FORMAT_R64G64B64A64_SINT,
295 DATA_FORMAT_R64G64B64A64_SFLOAT,
296 DATA_FORMAT_B10G11R11_UFLOAT_PACK32,
297 DATA_FORMAT_E5B9G9R9_UFLOAT_PACK32,
298 DATA_FORMAT_D16_UNORM,
299 DATA_FORMAT_X8_D24_UNORM_PACK32,
300 DATA_FORMAT_D32_SFLOAT,
301 DATA_FORMAT_S8_UINT,
302 DATA_FORMAT_D16_UNORM_S8_UINT,
303 DATA_FORMAT_D24_UNORM_S8_UINT,
304 DATA_FORMAT_D32_SFLOAT_S8_UINT,
305 DATA_FORMAT_BC1_RGB_UNORM_BLOCK,
306 DATA_FORMAT_BC1_RGB_SRGB_BLOCK,
307 DATA_FORMAT_BC1_RGBA_UNORM_BLOCK,
308 DATA_FORMAT_BC1_RGBA_SRGB_BLOCK,
309 DATA_FORMAT_BC2_UNORM_BLOCK,
310 DATA_FORMAT_BC2_SRGB_BLOCK,
311 DATA_FORMAT_BC3_UNORM_BLOCK,
312 DATA_FORMAT_BC3_SRGB_BLOCK,
313 DATA_FORMAT_BC4_UNORM_BLOCK,
314 DATA_FORMAT_BC4_SNORM_BLOCK,
315 DATA_FORMAT_BC5_UNORM_BLOCK,
316 DATA_FORMAT_BC5_SNORM_BLOCK,
317 DATA_FORMAT_BC6H_UFLOAT_BLOCK,
318 DATA_FORMAT_BC6H_SFLOAT_BLOCK,
319 DATA_FORMAT_BC7_UNORM_BLOCK,
320 DATA_FORMAT_BC7_SRGB_BLOCK,
321 DATA_FORMAT_ETC2_R8G8B8_UNORM_BLOCK,
322 DATA_FORMAT_ETC2_R8G8B8_SRGB_BLOCK,
323 DATA_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK,
324 DATA_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK,
325 DATA_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK,
326 DATA_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK,
327 DATA_FORMAT_EAC_R11_UNORM_BLOCK,
328 DATA_FORMAT_EAC_R11_SNORM_BLOCK,
329 DATA_FORMAT_EAC_R11G11_UNORM_BLOCK,
330 DATA_FORMAT_EAC_R11G11_SNORM_BLOCK,
331 DATA_FORMAT_ASTC_4x4_UNORM_BLOCK,
332 DATA_FORMAT_ASTC_4x4_SRGB_BLOCK,
333 DATA_FORMAT_ASTC_5x4_UNORM_BLOCK,
334 DATA_FORMAT_ASTC_5x4_SRGB_BLOCK,
335 DATA_FORMAT_ASTC_5x5_UNORM_BLOCK,
336 DATA_FORMAT_ASTC_5x5_SRGB_BLOCK,
337 DATA_FORMAT_ASTC_6x5_UNORM_BLOCK,
338 DATA_FORMAT_ASTC_6x5_SRGB_BLOCK,
339 DATA_FORMAT_ASTC_6x6_UNORM_BLOCK,
340 DATA_FORMAT_ASTC_6x6_SRGB_BLOCK,
341 DATA_FORMAT_ASTC_8x5_UNORM_BLOCK,
342 DATA_FORMAT_ASTC_8x5_SRGB_BLOCK,
343 DATA_FORMAT_ASTC_8x6_UNORM_BLOCK,
344 DATA_FORMAT_ASTC_8x6_SRGB_BLOCK,
345 DATA_FORMAT_ASTC_8x8_UNORM_BLOCK,
346 DATA_FORMAT_ASTC_8x8_SRGB_BLOCK,
347 DATA_FORMAT_ASTC_10x5_UNORM_BLOCK,
348 DATA_FORMAT_ASTC_10x5_SRGB_BLOCK,
349 DATA_FORMAT_ASTC_10x6_UNORM_BLOCK,
350 DATA_FORMAT_ASTC_10x6_SRGB_BLOCK,
351 DATA_FORMAT_ASTC_10x8_UNORM_BLOCK,
352 DATA_FORMAT_ASTC_10x8_SRGB_BLOCK,
353 DATA_FORMAT_ASTC_10x10_UNORM_BLOCK,
354 DATA_FORMAT_ASTC_10x10_SRGB_BLOCK,
355 DATA_FORMAT_ASTC_12x10_UNORM_BLOCK,
356 DATA_FORMAT_ASTC_12x10_SRGB_BLOCK,
357 DATA_FORMAT_ASTC_12x12_UNORM_BLOCK,
358 DATA_FORMAT_ASTC_12x12_SRGB_BLOCK,
359 DATA_FORMAT_G8B8G8R8_422_UNORM,
360 DATA_FORMAT_B8G8R8G8_422_UNORM,
361 DATA_FORMAT_G8_B8_R8_3PLANE_420_UNORM,
362 DATA_FORMAT_G8_B8R8_2PLANE_420_UNORM,
363 DATA_FORMAT_G8_B8_R8_3PLANE_422_UNORM,
364 DATA_FORMAT_G8_B8R8_2PLANE_422_UNORM,
365 DATA_FORMAT_G8_B8_R8_3PLANE_444_UNORM,
366 DATA_FORMAT_R10X6_UNORM_PACK16,
367 DATA_FORMAT_R10X6G10X6_UNORM_2PACK16,
368 DATA_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16,
369 DATA_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16,
370 DATA_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16,
371 DATA_FORMAT_G10X6_B10X6_R10X6_3PLANE_420_UNORM_3PACK16,
372 DATA_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16,
373 DATA_FORMAT_G10X6_B10X6_R10X6_3PLANE_422_UNORM_3PACK16,
374 DATA_FORMAT_G10X6_B10X6R10X6_2PLANE_422_UNORM_3PACK16,
375 DATA_FORMAT_G10X6_B10X6_R10X6_3PLANE_444_UNORM_3PACK16,
376 DATA_FORMAT_R12X4_UNORM_PACK16,
377 DATA_FORMAT_R12X4G12X4_UNORM_2PACK16,
378 DATA_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16,
379 DATA_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16,
380 DATA_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16,
381 DATA_FORMAT_G12X4_B12X4_R12X4_3PLANE_420_UNORM_3PACK16,
382 DATA_FORMAT_G12X4_B12X4R12X4_2PLANE_420_UNORM_3PACK16,
383 DATA_FORMAT_G12X4_B12X4_R12X4_3PLANE_422_UNORM_3PACK16,
384 DATA_FORMAT_G12X4_B12X4R12X4_2PLANE_422_UNORM_3PACK16,
385 DATA_FORMAT_G12X4_B12X4_R12X4_3PLANE_444_UNORM_3PACK16,
386 DATA_FORMAT_G16B16G16R16_422_UNORM,
387 DATA_FORMAT_B16G16R16G16_422_UNORM,
388 DATA_FORMAT_G16_B16_R16_3PLANE_420_UNORM,
389 DATA_FORMAT_G16_B16R16_2PLANE_420_UNORM,
390 DATA_FORMAT_G16_B16_R16_3PLANE_422_UNORM,
391 DATA_FORMAT_G16_B16R16_2PLANE_422_UNORM,
392 DATA_FORMAT_G16_B16_R16_3PLANE_444_UNORM,
393 DATA_FORMAT_MAX
394 };
395
396 /*****************/
397 /**** BARRIER ****/
398 /*****************/
399
400 enum BarrierMask {
401 BARRIER_MASK_VERTEX = 1,
402 BARRIER_MASK_FRAGMENT = 8,
403 BARRIER_MASK_COMPUTE = 2,
404 BARRIER_MASK_TRANSFER = 4,
405
406 BARRIER_MASK_RASTER = BARRIER_MASK_VERTEX | BARRIER_MASK_FRAGMENT, // 9,
407 BARRIER_MASK_ALL_BARRIERS = 0x7FFF, // all flags set
408 BARRIER_MASK_NO_BARRIER = 0x8000,
409 };
410
411 /*****************/
412 /**** TEXTURE ****/
413 /*****************/
414
415 enum TextureType {
416 TEXTURE_TYPE_1D,
417 TEXTURE_TYPE_2D,
418 TEXTURE_TYPE_3D,
419 TEXTURE_TYPE_CUBE,
420 TEXTURE_TYPE_1D_ARRAY,
421 TEXTURE_TYPE_2D_ARRAY,
422 TEXTURE_TYPE_CUBE_ARRAY,
423 TEXTURE_TYPE_MAX
424 };
425
426 enum TextureSamples {
427 TEXTURE_SAMPLES_1,
428 TEXTURE_SAMPLES_2,
429 TEXTURE_SAMPLES_4,
430 TEXTURE_SAMPLES_8,
431 TEXTURE_SAMPLES_16,
432 TEXTURE_SAMPLES_32,
433 TEXTURE_SAMPLES_64,
434 TEXTURE_SAMPLES_MAX
435 };
436
437 enum TextureUsageBits {
438 TEXTURE_USAGE_SAMPLING_BIT = (1 << 0),
439 TEXTURE_USAGE_COLOR_ATTACHMENT_BIT = (1 << 1),
440 TEXTURE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT = (1 << 2),
441 TEXTURE_USAGE_STORAGE_BIT = (1 << 3),
442 TEXTURE_USAGE_STORAGE_ATOMIC_BIT = (1 << 4),
443 TEXTURE_USAGE_CPU_READ_BIT = (1 << 5),
444 TEXTURE_USAGE_CAN_UPDATE_BIT = (1 << 6),
445 TEXTURE_USAGE_CAN_COPY_FROM_BIT = (1 << 7),
446 TEXTURE_USAGE_CAN_COPY_TO_BIT = (1 << 8),
447 TEXTURE_USAGE_INPUT_ATTACHMENT_BIT = (1 << 9),
448 TEXTURE_USAGE_VRS_ATTACHMENT_BIT = (1 << 10),
449 };
450
451 enum TextureSwizzle {
452 TEXTURE_SWIZZLE_IDENTITY,
453 TEXTURE_SWIZZLE_ZERO,
454 TEXTURE_SWIZZLE_ONE,
455 TEXTURE_SWIZZLE_R,
456 TEXTURE_SWIZZLE_G,
457 TEXTURE_SWIZZLE_B,
458 TEXTURE_SWIZZLE_A,
459 TEXTURE_SWIZZLE_MAX
460 };
461
462 struct TextureFormat {
463 DataFormat format;
464 uint32_t width;
465 uint32_t height;
466 uint32_t depth;
467 uint32_t array_layers;
468 uint32_t mipmaps;
469 TextureType texture_type;
470 TextureSamples samples;
471 uint32_t usage_bits;
472 Vector<DataFormat> shareable_formats;
473 bool is_resolve_buffer = false;
474
475 bool operator==(const TextureFormat &b) const {
476 if (format != b.format) {
477 return false;
478 } else if (width != b.width) {
479 return false;
480 } else if (height != b.height) {
481 return false;
482 } else if (depth != b.depth) {
483 return false;
484 } else if (array_layers != b.array_layers) {
485 return false;
486 } else if (mipmaps != b.mipmaps) {
487 return false;
488 } else if (texture_type != b.texture_type) {
489 return false;
490 } else if (samples != b.samples) {
491 return false;
492 } else if (usage_bits != b.usage_bits) {
493 return false;
494 } else if (shareable_formats != b.shareable_formats) {
495 return false;
496 } else {
497 return true;
498 }
499 }
500
501 TextureFormat() {
502 format = DATA_FORMAT_R8_UNORM;
503 width = 1;
504 height = 1;
505 depth = 1;
506 array_layers = 1;
507 mipmaps = 1;
508 texture_type = TEXTURE_TYPE_2D;
509 samples = TEXTURE_SAMPLES_1;
510 usage_bits = 0;
511 }
512 };
513
514 struct TextureView {
515 DataFormat format_override;
516 TextureSwizzle swizzle_r;
517 TextureSwizzle swizzle_g;
518 TextureSwizzle swizzle_b;
519 TextureSwizzle swizzle_a;
520
521 TextureView() {
522 format_override = DATA_FORMAT_MAX; //means, use same as format
523 swizzle_r = TEXTURE_SWIZZLE_R;
524 swizzle_g = TEXTURE_SWIZZLE_G;
525 swizzle_b = TEXTURE_SWIZZLE_B;
526 swizzle_a = TEXTURE_SWIZZLE_A;
527 }
528 };
529
530 virtual RID texture_create(const TextureFormat &p_format, const TextureView &p_view, const Vector<Vector<uint8_t>> &p_data = Vector<Vector<uint8_t>>()) = 0;
531 virtual RID texture_create_shared(const TextureView &p_view, RID p_with_texture) = 0;
532 virtual RID texture_create_from_extension(TextureType p_type, DataFormat p_format, TextureSamples p_samples, uint64_t p_flags, uint64_t p_image, uint64_t p_width, uint64_t p_height, uint64_t p_depth, uint64_t p_layers) = 0;
533
534 enum TextureSliceType {
535 TEXTURE_SLICE_2D,
536 TEXTURE_SLICE_CUBEMAP,
537 TEXTURE_SLICE_3D,
538 TEXTURE_SLICE_2D_ARRAY,
539 };
540
541 virtual RID texture_create_shared_from_slice(const TextureView &p_view, RID p_with_texture, uint32_t p_layer, uint32_t p_mipmap, uint32_t p_mipmaps = 1, TextureSliceType p_slice_type = TEXTURE_SLICE_2D, uint32_t p_layers = 0) = 0;
542
543 virtual Error texture_update(RID p_texture, uint32_t p_layer, const Vector<uint8_t> &p_data, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
544 virtual Vector<uint8_t> texture_get_data(RID p_texture, uint32_t p_layer) = 0; // CPU textures will return immediately, while GPU textures will most likely force a flush
545
546 virtual bool texture_is_format_supported_for_usage(DataFormat p_format, BitField<RenderingDevice::TextureUsageBits> p_usage) const = 0;
547 virtual bool texture_is_shared(RID p_texture) = 0;
548 virtual bool texture_is_valid(RID p_texture) = 0;
549 virtual TextureFormat texture_get_format(RID p_texture) = 0;
550 virtual Size2i texture_size(RID p_texture) = 0;
551 virtual uint64_t texture_get_native_handle(RID p_texture) = 0;
552
553 virtual Error texture_copy(RID p_from_texture, RID p_to_texture, const Vector3 &p_from, const Vector3 &p_to, const Vector3 &p_size, uint32_t p_src_mipmap, uint32_t p_dst_mipmap, uint32_t p_src_layer, uint32_t p_dst_layer, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
554 virtual Error texture_clear(RID p_texture, const Color &p_color, uint32_t p_base_mipmap, uint32_t p_mipmaps, uint32_t p_base_layer, uint32_t p_layers, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
555 virtual Error texture_resolve_multisample(RID p_from_texture, RID p_to_texture, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
556
557 /*********************/
558 /**** FRAMEBUFFER ****/
559 /*********************/
560
561 struct AttachmentFormat {
562 enum { UNUSED_ATTACHMENT = 0xFFFFFFFF };
563 DataFormat format;
564 TextureSamples samples;
565 uint32_t usage_flags;
566 AttachmentFormat() {
567 format = DATA_FORMAT_R8G8B8A8_UNORM;
568 samples = TEXTURE_SAMPLES_1;
569 usage_flags = 0;
570 }
571 };
572
573 typedef int64_t FramebufferFormatID;
574
575 // This ID is warranted to be unique for the same formats, does not need to be freed
576 virtual FramebufferFormatID framebuffer_format_create(const Vector<AttachmentFormat> &p_format, uint32_t p_view_count = 1) = 0;
577 struct FramebufferPass {
578 enum {
579 ATTACHMENT_UNUSED = -1
580 };
581 Vector<int32_t> color_attachments;
582 Vector<int32_t> input_attachments;
583 Vector<int32_t> resolve_attachments;
584 Vector<int32_t> preserve_attachments;
585 int32_t depth_attachment = ATTACHMENT_UNUSED;
586 int32_t vrs_attachment = ATTACHMENT_UNUSED; // density map for VRS, only used if supported
587 };
588
589 virtual FramebufferFormatID framebuffer_format_create_multipass(const Vector<AttachmentFormat> &p_attachments, const Vector<FramebufferPass> &p_passes, uint32_t p_view_count = 1) = 0;
590 virtual FramebufferFormatID framebuffer_format_create_empty(TextureSamples p_samples = TEXTURE_SAMPLES_1) = 0;
591 virtual TextureSamples framebuffer_format_get_texture_samples(FramebufferFormatID p_format, uint32_t p_pass = 0) = 0;
592
593 virtual RID framebuffer_create(const Vector<RID> &p_texture_attachments, FramebufferFormatID p_format_check = INVALID_ID, uint32_t p_view_count = 1) = 0;
594 virtual RID framebuffer_create_multipass(const Vector<RID> &p_texture_attachments, const Vector<FramebufferPass> &p_passes, FramebufferFormatID p_format_check = INVALID_ID, uint32_t p_view_count = 1) = 0;
595 virtual RID framebuffer_create_empty(const Size2i &p_size, TextureSamples p_samples = TEXTURE_SAMPLES_1, FramebufferFormatID p_format_check = INVALID_ID) = 0;
596 virtual bool framebuffer_is_valid(RID p_framebuffer) const = 0;
597 virtual void framebuffer_set_invalidation_callback(RID p_framebuffer, InvalidationCallback p_callback, void *p_userdata) = 0;
598
599 virtual FramebufferFormatID framebuffer_get_format(RID p_framebuffer) = 0;
600
601 /*****************/
602 /**** SAMPLER ****/
603 /*****************/
604
605 enum SamplerFilter {
606 SAMPLER_FILTER_NEAREST,
607 SAMPLER_FILTER_LINEAR,
608 };
609
610 enum SamplerRepeatMode {
611 SAMPLER_REPEAT_MODE_REPEAT,
612 SAMPLER_REPEAT_MODE_MIRRORED_REPEAT,
613 SAMPLER_REPEAT_MODE_CLAMP_TO_EDGE,
614 SAMPLER_REPEAT_MODE_CLAMP_TO_BORDER,
615 SAMPLER_REPEAT_MODE_MIRROR_CLAMP_TO_EDGE,
616 SAMPLER_REPEAT_MODE_MAX
617 };
618
619 enum SamplerBorderColor {
620 SAMPLER_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK,
621 SAMPLER_BORDER_COLOR_INT_TRANSPARENT_BLACK,
622 SAMPLER_BORDER_COLOR_FLOAT_OPAQUE_BLACK,
623 SAMPLER_BORDER_COLOR_INT_OPAQUE_BLACK,
624 SAMPLER_BORDER_COLOR_FLOAT_OPAQUE_WHITE,
625 SAMPLER_BORDER_COLOR_INT_OPAQUE_WHITE,
626 SAMPLER_BORDER_COLOR_MAX
627 };
628
629 struct SamplerState {
630 SamplerFilter mag_filter;
631 SamplerFilter min_filter;
632 SamplerFilter mip_filter;
633 SamplerRepeatMode repeat_u;
634 SamplerRepeatMode repeat_v;
635 SamplerRepeatMode repeat_w;
636 float lod_bias;
637 bool use_anisotropy;
638 float anisotropy_max;
639 bool enable_compare;
640 CompareOperator compare_op;
641 float min_lod;
642 float max_lod;
643 SamplerBorderColor border_color;
644 bool unnormalized_uvw;
645
646 SamplerState() {
647 mag_filter = SAMPLER_FILTER_NEAREST;
648 min_filter = SAMPLER_FILTER_NEAREST;
649 mip_filter = SAMPLER_FILTER_NEAREST;
650 repeat_u = SAMPLER_REPEAT_MODE_CLAMP_TO_EDGE;
651 repeat_v = SAMPLER_REPEAT_MODE_CLAMP_TO_EDGE;
652 repeat_w = SAMPLER_REPEAT_MODE_CLAMP_TO_EDGE;
653 lod_bias = 0;
654 use_anisotropy = false;
655 anisotropy_max = 1.0;
656 enable_compare = false;
657 compare_op = COMPARE_OP_ALWAYS;
658 min_lod = 0;
659 max_lod = 1e20; //something very large should do
660 border_color = SAMPLER_BORDER_COLOR_FLOAT_OPAQUE_BLACK;
661 unnormalized_uvw = false;
662 }
663 };
664
665 virtual RID sampler_create(const SamplerState &p_state) = 0;
666 virtual bool sampler_is_format_supported_for_filter(DataFormat p_format, SamplerFilter p_sampler_filter) const = 0;
667
668 /**********************/
669 /**** VERTEX ARRAY ****/
670 /**********************/
671
672 enum VertexFrequency {
673 VERTEX_FREQUENCY_VERTEX,
674 VERTEX_FREQUENCY_INSTANCE,
675 };
676
677 struct VertexAttribute {
678 uint32_t location; //shader location
679 uint32_t offset;
680 DataFormat format;
681 uint32_t stride;
682 VertexFrequency frequency;
683 VertexAttribute() {
684 location = 0;
685 offset = 0;
686 stride = 0;
687 format = DATA_FORMAT_MAX;
688 frequency = VERTEX_FREQUENCY_VERTEX;
689 }
690 };
691 virtual RID vertex_buffer_create(uint32_t p_size_bytes, const Vector<uint8_t> &p_data = Vector<uint8_t>(), bool p_use_as_storage = false) = 0;
692
693 typedef int64_t VertexFormatID;
694
695 // This ID is warranted to be unique for the same formats, does not need to be freed
696 virtual VertexFormatID vertex_format_create(const Vector<VertexAttribute> &p_vertex_formats) = 0;
697 virtual RID vertex_array_create(uint32_t p_vertex_count, VertexFormatID p_vertex_format, const Vector<RID> &p_src_buffers, const Vector<uint64_t> &p_offsets = Vector<uint64_t>()) = 0;
698
699 enum IndexBufferFormat {
700 INDEX_BUFFER_FORMAT_UINT16,
701 INDEX_BUFFER_FORMAT_UINT32,
702 };
703
704 virtual RID index_buffer_create(uint32_t p_size_indices, IndexBufferFormat p_format, const Vector<uint8_t> &p_data = Vector<uint8_t>(), bool p_use_restart_indices = false) = 0;
705 virtual RID index_array_create(RID p_index_buffer, uint32_t p_index_offset, uint32_t p_index_count) = 0;
706
707 /****************/
708 /**** SHADER ****/
709 /****************/
710
711 const Capabilities *get_device_capabilities() const { return &device_capabilities; };
712
713 enum Features {
714 SUPPORTS_MULTIVIEW,
715 SUPPORTS_FSR_HALF_FLOAT,
716 SUPPORTS_ATTACHMENT_VRS,
717 // If not supported, a fragment shader with only side effets (i.e., writes to buffers, but doesn't output to attachments), may be optimized down to no-op by the GPU driver.
718 SUPPORTS_FRAGMENT_SHADER_WITH_ONLY_SIDE_EFFECTS,
719 };
720 virtual bool has_feature(const Features p_feature) const = 0;
721
722 virtual Vector<uint8_t> shader_compile_spirv_from_source(ShaderStage p_stage, const String &p_source_code, ShaderLanguage p_language = SHADER_LANGUAGE_GLSL, String *r_error = nullptr, bool p_allow_cache = true);
723 virtual String shader_get_spirv_cache_key() const;
724
725 static void shader_set_compile_to_spirv_function(ShaderCompileToSPIRVFunction p_function);
726 static void shader_set_spirv_cache_function(ShaderCacheFunction p_function);
727 static void shader_set_get_cache_key_function(ShaderSPIRVGetCacheKeyFunction p_function);
728
729 struct ShaderStageSPIRVData {
730 ShaderStage shader_stage;
731 Vector<uint8_t> spir_v;
732
733 ShaderStageSPIRVData() {
734 shader_stage = SHADER_STAGE_VERTEX;
735 }
736 };
737
738 virtual String shader_get_binary_cache_key() const = 0;
739 virtual Vector<uint8_t> shader_compile_binary_from_spirv(const Vector<ShaderStageSPIRVData> &p_spirv, const String &p_shader_name = "") = 0;
740
741 virtual RID shader_create_from_spirv(const Vector<ShaderStageSPIRVData> &p_spirv, const String &p_shader_name = "");
742 virtual RID shader_create_from_bytecode(const Vector<uint8_t> &p_shader_binary, RID p_placeholder = RID()) = 0;
743 virtual RID shader_create_placeholder() = 0;
744
745 virtual uint32_t shader_get_vertex_input_attribute_mask(RID p_shader) = 0;
746
747 /******************/
748 /**** UNIFORMS ****/
749 /******************/
750
751 enum UniformType {
752 UNIFORM_TYPE_SAMPLER, //for sampling only (sampler GLSL type)
753 UNIFORM_TYPE_SAMPLER_WITH_TEXTURE, // for sampling only, but includes a texture, (samplerXX GLSL type), first a sampler then a texture
754 UNIFORM_TYPE_TEXTURE, //only texture, (textureXX GLSL type)
755 UNIFORM_TYPE_IMAGE, // storage image (imageXX GLSL type), for compute mostly
756 UNIFORM_TYPE_TEXTURE_BUFFER, // buffer texture (or TBO, textureBuffer type)
757 UNIFORM_TYPE_SAMPLER_WITH_TEXTURE_BUFFER, // buffer texture with a sampler(or TBO, samplerBuffer type)
758 UNIFORM_TYPE_IMAGE_BUFFER, //texel buffer, (imageBuffer type), for compute mostly
759 UNIFORM_TYPE_UNIFORM_BUFFER, //regular uniform buffer (or UBO).
760 UNIFORM_TYPE_STORAGE_BUFFER, //storage buffer ("buffer" qualifier) like UBO, but supports storage, for compute mostly
761 UNIFORM_TYPE_INPUT_ATTACHMENT, //used for sub-pass read/write, for mobile mostly
762 UNIFORM_TYPE_MAX
763 };
764
765 enum StorageBufferUsage {
766 STORAGE_BUFFER_USAGE_DISPATCH_INDIRECT = 1,
767 };
768
769 virtual RID uniform_buffer_create(uint32_t p_size_bytes, const Vector<uint8_t> &p_data = Vector<uint8_t>()) = 0;
770 virtual RID storage_buffer_create(uint32_t p_size, const Vector<uint8_t> &p_data = Vector<uint8_t>(), BitField<StorageBufferUsage> p_usage = 0) = 0;
771 virtual RID texture_buffer_create(uint32_t p_size_elements, DataFormat p_format, const Vector<uint8_t> &p_data = Vector<uint8_t>()) = 0;
772
773 struct Uniform {
774 UniformType uniform_type;
775 int binding; // Binding index as specified in shader.
776
777 private:
778 // In most cases only one ID is provided per binding, so avoid allocating memory unnecessarily for performance.
779 RID id; // If only one is provided, this is used.
780 Vector<RID> ids; // If multiple ones are provided, this is used instead.
781
782 public:
783 _FORCE_INLINE_ uint32_t get_id_count() const {
784 return (id.is_valid() ? 1 : ids.size());
785 }
786
787 _FORCE_INLINE_ RID get_id(uint32_t p_idx) const {
788 if (id.is_valid()) {
789 ERR_FAIL_COND_V(p_idx != 0, RID());
790 return id;
791 } else {
792 return ids[p_idx];
793 }
794 }
795 _FORCE_INLINE_ void set_id(uint32_t p_idx, RID p_id) {
796 if (id.is_valid()) {
797 ERR_FAIL_COND(p_idx != 0);
798 id = p_id;
799 } else {
800 ids.write[p_idx] = p_id;
801 }
802 }
803
804 _FORCE_INLINE_ void append_id(RID p_id) {
805 if (ids.is_empty()) {
806 if (id == RID()) {
807 id = p_id;
808 } else {
809 ids.push_back(id);
810 ids.push_back(p_id);
811 id = RID();
812 }
813 } else {
814 ids.push_back(p_id);
815 }
816 }
817
818 _FORCE_INLINE_ void clear_ids() {
819 id = RID();
820 ids.clear();
821 }
822
823 _FORCE_INLINE_ Uniform(UniformType p_type, int p_binding, RID p_id) {
824 uniform_type = p_type;
825 binding = p_binding;
826 id = p_id;
827 }
828 _FORCE_INLINE_ Uniform(UniformType p_type, int p_binding, const Vector<RID> &p_ids) {
829 uniform_type = p_type;
830 binding = p_binding;
831 ids = p_ids;
832 }
833 _FORCE_INLINE_ Uniform() {
834 uniform_type = UNIFORM_TYPE_IMAGE;
835 binding = 0;
836 }
837 };
838
839 virtual RID uniform_set_create(const Vector<Uniform> &p_uniforms, RID p_shader, uint32_t p_shader_set) = 0;
840 virtual bool uniform_set_is_valid(RID p_uniform_set) = 0;
841 virtual void uniform_set_set_invalidation_callback(RID p_uniform_set, InvalidationCallback p_callback, void *p_userdata) = 0;
842
843 virtual Error buffer_copy(RID p_src_buffer, RID p_dst_buffer, uint32_t p_src_offset, uint32_t p_dst_offset, uint32_t p_size, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
844 virtual Error buffer_update(RID p_buffer, uint32_t p_offset, uint32_t p_size, const void *p_data, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
845 virtual Error buffer_clear(RID p_buffer, uint32_t p_offset, uint32_t p_size, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
846 virtual Vector<uint8_t> buffer_get_data(RID p_buffer, uint32_t p_offset = 0, uint32_t p_size = 0) = 0; // This causes stall, only use to retrieve large buffers for saving.
847
848 /******************************************/
849 /**** PIPELINE SPECIALIZATION CONSTANT ****/
850 /******************************************/
851
852 enum PipelineSpecializationConstantType {
853 PIPELINE_SPECIALIZATION_CONSTANT_TYPE_BOOL,
854 PIPELINE_SPECIALIZATION_CONSTANT_TYPE_INT,
855 PIPELINE_SPECIALIZATION_CONSTANT_TYPE_FLOAT,
856 };
857
858 struct PipelineSpecializationConstant {
859 PipelineSpecializationConstantType type;
860 uint32_t constant_id;
861 union {
862 uint32_t int_value;
863 float float_value;
864 bool bool_value;
865 };
866
867 PipelineSpecializationConstant() {
868 type = PIPELINE_SPECIALIZATION_CONSTANT_TYPE_BOOL;
869 constant_id = 0;
870 int_value = 0;
871 }
872 };
873
874 /*************************/
875 /**** RENDER PIPELINE ****/
876 /*************************/
877
878 enum RenderPrimitive {
879 RENDER_PRIMITIVE_POINTS,
880 RENDER_PRIMITIVE_LINES,
881 RENDER_PRIMITIVE_LINES_WITH_ADJACENCY,
882 RENDER_PRIMITIVE_LINESTRIPS,
883 RENDER_PRIMITIVE_LINESTRIPS_WITH_ADJACENCY,
884 RENDER_PRIMITIVE_TRIANGLES,
885 RENDER_PRIMITIVE_TRIANGLES_WITH_ADJACENCY,
886 RENDER_PRIMITIVE_TRIANGLE_STRIPS,
887 RENDER_PRIMITIVE_TRIANGLE_STRIPS_WITH_AJACENCY,
888 RENDER_PRIMITIVE_TRIANGLE_STRIPS_WITH_RESTART_INDEX,
889 RENDER_PRIMITIVE_TESSELATION_PATCH,
890 RENDER_PRIMITIVE_MAX
891 };
892
893 //disable optimization, tessellate control points
894
895 enum PolygonCullMode {
896 POLYGON_CULL_DISABLED,
897 POLYGON_CULL_FRONT,
898 POLYGON_CULL_BACK,
899 };
900
901 enum PolygonFrontFace {
902 POLYGON_FRONT_FACE_CLOCKWISE,
903 POLYGON_FRONT_FACE_COUNTER_CLOCKWISE,
904 };
905
906 enum StencilOperation {
907 STENCIL_OP_KEEP,
908 STENCIL_OP_ZERO,
909 STENCIL_OP_REPLACE,
910 STENCIL_OP_INCREMENT_AND_CLAMP,
911 STENCIL_OP_DECREMENT_AND_CLAMP,
912 STENCIL_OP_INVERT,
913 STENCIL_OP_INCREMENT_AND_WRAP,
914 STENCIL_OP_DECREMENT_AND_WRAP,
915 STENCIL_OP_MAX //not an actual operator, just the amount of operators :D
916 };
917
918 enum LogicOperation {
919 LOGIC_OP_CLEAR,
920 LOGIC_OP_AND,
921 LOGIC_OP_AND_REVERSE,
922 LOGIC_OP_COPY,
923 LOGIC_OP_AND_INVERTED,
924 LOGIC_OP_NO_OP,
925 LOGIC_OP_XOR,
926 LOGIC_OP_OR,
927 LOGIC_OP_NOR,
928 LOGIC_OP_EQUIVALENT,
929 LOGIC_OP_INVERT,
930 LOGIC_OP_OR_REVERSE,
931 LOGIC_OP_COPY_INVERTED,
932 LOGIC_OP_OR_INVERTED,
933 LOGIC_OP_NAND,
934 LOGIC_OP_SET,
935 LOGIC_OP_MAX //not an actual operator, just the amount of operators :D
936 };
937
938 enum BlendFactor {
939 BLEND_FACTOR_ZERO,
940 BLEND_FACTOR_ONE,
941 BLEND_FACTOR_SRC_COLOR,
942 BLEND_FACTOR_ONE_MINUS_SRC_COLOR,
943 BLEND_FACTOR_DST_COLOR,
944 BLEND_FACTOR_ONE_MINUS_DST_COLOR,
945 BLEND_FACTOR_SRC_ALPHA,
946 BLEND_FACTOR_ONE_MINUS_SRC_ALPHA,
947 BLEND_FACTOR_DST_ALPHA,
948 BLEND_FACTOR_ONE_MINUS_DST_ALPHA,
949 BLEND_FACTOR_CONSTANT_COLOR,
950 BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR,
951 BLEND_FACTOR_CONSTANT_ALPHA,
952 BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA,
953 BLEND_FACTOR_SRC_ALPHA_SATURATE,
954 BLEND_FACTOR_SRC1_COLOR,
955 BLEND_FACTOR_ONE_MINUS_SRC1_COLOR,
956 BLEND_FACTOR_SRC1_ALPHA,
957 BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA,
958 BLEND_FACTOR_MAX
959 };
960
961 enum BlendOperation {
962 BLEND_OP_ADD,
963 BLEND_OP_SUBTRACT,
964 BLEND_OP_REVERSE_SUBTRACT,
965 BLEND_OP_MINIMUM,
966 BLEND_OP_MAXIMUM, //yes this one is an actual operator
967 BLEND_OP_MAX //not an actual operator, just the amount of operators :D
968 };
969
970 struct PipelineRasterizationState {
971 bool enable_depth_clamp;
972 bool discard_primitives;
973 bool wireframe;
974 PolygonCullMode cull_mode;
975 PolygonFrontFace front_face;
976 bool depth_bias_enabled;
977 float depth_bias_constant_factor;
978 float depth_bias_clamp;
979 float depth_bias_slope_factor;
980 float line_width;
981 uint32_t patch_control_points;
982 PipelineRasterizationState() {
983 enable_depth_clamp = false;
984 discard_primitives = false;
985 wireframe = false;
986 cull_mode = POLYGON_CULL_DISABLED;
987 front_face = POLYGON_FRONT_FACE_CLOCKWISE;
988 depth_bias_enabled = false;
989 depth_bias_constant_factor = 0;
990 depth_bias_clamp = 0;
991 depth_bias_slope_factor = 0;
992 line_width = 1.0;
993 patch_control_points = 1;
994 }
995 };
996
997 struct PipelineMultisampleState {
998 TextureSamples sample_count;
999 bool enable_sample_shading;
1000 float min_sample_shading;
1001 Vector<uint32_t> sample_mask;
1002 bool enable_alpha_to_coverage;
1003 bool enable_alpha_to_one;
1004
1005 PipelineMultisampleState() {
1006 sample_count = TEXTURE_SAMPLES_1;
1007 enable_sample_shading = false;
1008 min_sample_shading = 0;
1009 enable_alpha_to_coverage = false;
1010 enable_alpha_to_one = false;
1011 }
1012 };
1013
1014 struct PipelineDepthStencilState {
1015 bool enable_depth_test;
1016 bool enable_depth_write;
1017 CompareOperator depth_compare_operator;
1018 bool enable_depth_range;
1019 float depth_range_min;
1020 float depth_range_max;
1021 bool enable_stencil;
1022
1023 struct StencilOperationState {
1024 StencilOperation fail;
1025 StencilOperation pass;
1026 StencilOperation depth_fail;
1027 CompareOperator compare;
1028 uint32_t compare_mask;
1029 uint32_t write_mask;
1030 uint32_t reference;
1031
1032 StencilOperationState() {
1033 fail = STENCIL_OP_ZERO;
1034 pass = STENCIL_OP_ZERO;
1035 depth_fail = STENCIL_OP_ZERO;
1036 compare = COMPARE_OP_ALWAYS;
1037 compare_mask = 0;
1038 write_mask = 0;
1039 reference = 0;
1040 }
1041 };
1042
1043 StencilOperationState front_op;
1044 StencilOperationState back_op;
1045
1046 PipelineDepthStencilState() {
1047 enable_depth_test = false;
1048 enable_depth_write = false;
1049 depth_compare_operator = COMPARE_OP_ALWAYS;
1050 enable_depth_range = false;
1051 depth_range_min = 0;
1052 depth_range_max = 0;
1053 enable_stencil = false;
1054 }
1055 };
1056
1057 struct PipelineColorBlendState {
1058 bool enable_logic_op;
1059 LogicOperation logic_op;
1060 struct Attachment {
1061 bool enable_blend;
1062 BlendFactor src_color_blend_factor;
1063 BlendFactor dst_color_blend_factor;
1064 BlendOperation color_blend_op;
1065 BlendFactor src_alpha_blend_factor;
1066 BlendFactor dst_alpha_blend_factor;
1067 BlendOperation alpha_blend_op;
1068 bool write_r;
1069 bool write_g;
1070 bool write_b;
1071 bool write_a;
1072 Attachment() {
1073 enable_blend = false;
1074 src_color_blend_factor = BLEND_FACTOR_ZERO;
1075 dst_color_blend_factor = BLEND_FACTOR_ZERO;
1076 color_blend_op = BLEND_OP_ADD;
1077 src_alpha_blend_factor = BLEND_FACTOR_ZERO;
1078 dst_alpha_blend_factor = BLEND_FACTOR_ZERO;
1079 alpha_blend_op = BLEND_OP_ADD;
1080 write_r = true;
1081 write_g = true;
1082 write_b = true;
1083 write_a = true;
1084 }
1085 };
1086
1087 static PipelineColorBlendState create_disabled(int p_attachments = 1) {
1088 PipelineColorBlendState bs;
1089 for (int i = 0; i < p_attachments; i++) {
1090 bs.attachments.push_back(Attachment());
1091 }
1092 return bs;
1093 }
1094
1095 static PipelineColorBlendState create_blend(int p_attachments = 1) {
1096 PipelineColorBlendState bs;
1097 for (int i = 0; i < p_attachments; i++) {
1098 Attachment ba;
1099 ba.enable_blend = true;
1100 ba.src_color_blend_factor = BLEND_FACTOR_SRC_ALPHA;
1101 ba.dst_color_blend_factor = BLEND_FACTOR_ONE_MINUS_SRC_ALPHA;
1102 ba.src_alpha_blend_factor = BLEND_FACTOR_SRC_ALPHA;
1103 ba.dst_alpha_blend_factor = BLEND_FACTOR_ONE_MINUS_SRC_ALPHA;
1104
1105 bs.attachments.push_back(ba);
1106 }
1107 return bs;
1108 }
1109
1110 Vector<Attachment> attachments; //one per render target texture
1111 Color blend_constant;
1112
1113 PipelineColorBlendState() {
1114 enable_logic_op = false;
1115 logic_op = LOGIC_OP_CLEAR;
1116 }
1117 };
1118
1119 enum PipelineDynamicStateFlags {
1120 DYNAMIC_STATE_LINE_WIDTH = (1 << 0),
1121 DYNAMIC_STATE_DEPTH_BIAS = (1 << 1),
1122 DYNAMIC_STATE_BLEND_CONSTANTS = (1 << 2),
1123 DYNAMIC_STATE_DEPTH_BOUNDS = (1 << 3),
1124 DYNAMIC_STATE_STENCIL_COMPARE_MASK = (1 << 4),
1125 DYNAMIC_STATE_STENCIL_WRITE_MASK = (1 << 5),
1126 DYNAMIC_STATE_STENCIL_REFERENCE = (1 << 6),
1127 };
1128
1129 virtual bool render_pipeline_is_valid(RID p_pipeline) = 0;
1130 virtual RID render_pipeline_create(RID p_shader, FramebufferFormatID p_framebuffer_format, VertexFormatID p_vertex_format, RenderPrimitive p_render_primitive, const PipelineRasterizationState &p_rasterization_state, const PipelineMultisampleState &p_multisample_state, const PipelineDepthStencilState &p_depth_stencil_state, const PipelineColorBlendState &p_blend_state, BitField<PipelineDynamicStateFlags> p_dynamic_state_flags = 0, uint32_t p_for_render_pass = 0, const Vector<PipelineSpecializationConstant> &p_specialization_constants = Vector<PipelineSpecializationConstant>()) = 0;
1131
1132 /**************************/
1133 /**** COMPUTE PIPELINE ****/
1134 /**************************/
1135
1136 virtual RID compute_pipeline_create(RID p_shader, const Vector<PipelineSpecializationConstant> &p_specialization_constants = Vector<PipelineSpecializationConstant>()) = 0;
1137 virtual bool compute_pipeline_is_valid(RID p_pipeline) = 0;
1138
1139 /****************/
1140 /**** SCREEN ****/
1141 /****************/
1142
1143 virtual int screen_get_width(DisplayServer::WindowID p_screen = 0) const = 0;
1144 virtual int screen_get_height(DisplayServer::WindowID p_screen = 0) const = 0;
1145 virtual FramebufferFormatID screen_get_framebuffer_format() const = 0;
1146
1147 /********************/
1148 /**** DRAW LISTS ****/
1149 /********************/
1150
1151 enum InitialAction {
1152 INITIAL_ACTION_CLEAR, // Start rendering and clear the whole framebuffer.
1153 INITIAL_ACTION_CLEAR_REGION, // Start rendering and clear the framebuffer in the specified region.
1154 INITIAL_ACTION_CLEAR_REGION_CONTINUE, // Continue rendering and clear the framebuffer in the specified region. Framebuffer must have been left in `FINAL_ACTION_CONTINUE` state as the final action previously.
1155 INITIAL_ACTION_KEEP, // Start rendering, but keep attached color texture contents. If the framebuffer was previously used to read in a shader, this will automatically insert a layout transition.
1156 INITIAL_ACTION_DROP, // Start rendering, ignore what is there; write above it. In general, this is the fastest option when you will be writing every single pixel and you don't need a clear color.
1157 INITIAL_ACTION_CONTINUE, // Continue rendering. Framebuffer must have been left in `FINAL_ACTION_CONTINUE` state as the final action previously.
1158 INITIAL_ACTION_MAX
1159 };
1160
1161 enum FinalAction {
1162 FINAL_ACTION_READ, // Store the texture for reading and make it read-only if it has the `TEXTURE_USAGE_SAMPLING_BIT` bit (only applies to color, depth and stencil attachments).
1163 FINAL_ACTION_DISCARD, // Discard the texture data and make it read-only if it has the `TEXTURE_USAGE_SAMPLING_BIT` bit (only applies to color, depth and stencil attachments).
1164 FINAL_ACTION_CONTINUE, // Store the texture and continue for further processing. Similar to `FINAL_ACTION_READ`, but does not make the texture read-only if it has the `TEXTURE_USAGE_SAMPLING_BIT` bit.
1165 FINAL_ACTION_MAX
1166 };
1167
1168 typedef int64_t DrawListID;
1169
1170 virtual DrawListID draw_list_begin_for_screen(DisplayServer::WindowID p_screen = 0, const Color &p_clear_color = Color()) = 0;
1171 virtual DrawListID draw_list_begin(RID p_framebuffer, InitialAction p_initial_color_action, FinalAction p_final_color_action, InitialAction p_initial_depth_action, FinalAction p_final_depth_action, const Vector<Color> &p_clear_color_values = Vector<Color>(), float p_clear_depth = 1.0, uint32_t p_clear_stencil = 0, const Rect2 &p_region = Rect2(), const Vector<RID> &p_storage_textures = Vector<RID>()) = 0;
1172 virtual Error draw_list_begin_split(RID p_framebuffer, uint32_t p_splits, DrawListID *r_split_ids, InitialAction p_initial_color_action, FinalAction p_final_color_action, InitialAction p_initial_depth_action, FinalAction p_final_depth_action, const Vector<Color> &p_clear_color_values = Vector<Color>(), float p_clear_depth = 1.0, uint32_t p_clear_stencil = 0, const Rect2 &p_region = Rect2(), const Vector<RID> &p_storage_textures = Vector<RID>()) = 0;
1173
1174 virtual void draw_list_set_blend_constants(DrawListID p_list, const Color &p_color) = 0;
1175 virtual void draw_list_bind_render_pipeline(DrawListID p_list, RID p_render_pipeline) = 0;
1176 virtual void draw_list_bind_uniform_set(DrawListID p_list, RID p_uniform_set, uint32_t p_index) = 0;
1177 virtual void draw_list_bind_vertex_array(DrawListID p_list, RID p_vertex_array) = 0;
1178 virtual void draw_list_bind_index_array(DrawListID p_list, RID p_index_array) = 0;
1179 virtual void draw_list_set_line_width(DrawListID p_list, float p_width) = 0;
1180 virtual void draw_list_set_push_constant(DrawListID p_list, const void *p_data, uint32_t p_data_size) = 0;
1181
1182 virtual void draw_list_draw(DrawListID p_list, bool p_use_indices, uint32_t p_instances = 1, uint32_t p_procedural_vertices = 0) = 0;
1183
1184 virtual void draw_list_enable_scissor(DrawListID p_list, const Rect2 &p_rect) = 0;
1185 virtual void draw_list_disable_scissor(DrawListID p_list) = 0;
1186
1187 virtual uint32_t draw_list_get_current_pass() = 0;
1188 virtual DrawListID draw_list_switch_to_next_pass() = 0;
1189 virtual Error draw_list_switch_to_next_pass_split(uint32_t p_splits, DrawListID *r_split_ids) = 0;
1190
1191 virtual void draw_list_end(BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
1192
1193 /***********************/
1194 /**** COMPUTE LISTS ****/
1195 /***********************/
1196
1197 typedef int64_t ComputeListID;
1198
1199 virtual ComputeListID compute_list_begin(bool p_allow_draw_overlap = false) = 0;
1200 virtual void compute_list_bind_compute_pipeline(ComputeListID p_list, RID p_compute_pipeline) = 0;
1201 virtual void compute_list_bind_uniform_set(ComputeListID p_list, RID p_uniform_set, uint32_t p_index) = 0;
1202 virtual void compute_list_set_push_constant(ComputeListID p_list, const void *p_data, uint32_t p_data_size) = 0;
1203 virtual void compute_list_dispatch(ComputeListID p_list, uint32_t p_x_groups, uint32_t p_y_groups, uint32_t p_z_groups) = 0;
1204 virtual void compute_list_dispatch_threads(ComputeListID p_list, uint32_t p_x_threads, uint32_t p_y_threads, uint32_t p_z_threads) = 0;
1205 virtual void compute_list_dispatch_indirect(ComputeListID p_list, RID p_buffer, uint32_t p_offset) = 0;
1206 virtual void compute_list_add_barrier(ComputeListID p_list) = 0;
1207
1208 virtual void compute_list_end(BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS) = 0;
1209
1210 virtual void barrier(BitField<BarrierMask> p_from = BARRIER_MASK_ALL_BARRIERS, BitField<BarrierMask> p_to = BARRIER_MASK_ALL_BARRIERS) = 0;
1211 virtual void full_barrier() = 0;
1212
1213 /***************/
1214 /**** FREE! ****/
1215 /***************/
1216
1217 virtual void free(RID p_id) = 0;
1218
1219 /****************/
1220 /**** Timing ****/
1221 /****************/
1222
1223 virtual void capture_timestamp(const String &p_name) = 0;
1224 virtual uint32_t get_captured_timestamps_count() const = 0;
1225 virtual uint64_t get_captured_timestamps_frame() const = 0;
1226 virtual uint64_t get_captured_timestamp_gpu_time(uint32_t p_index) const = 0;
1227 virtual uint64_t get_captured_timestamp_cpu_time(uint32_t p_index) const = 0;
1228 virtual String get_captured_timestamp_name(uint32_t p_index) const = 0;
1229
1230 /****************/
1231 /**** LIMITS ****/
1232 /****************/
1233
1234 enum Limit {
1235 LIMIT_MAX_BOUND_UNIFORM_SETS,
1236 LIMIT_MAX_FRAMEBUFFER_COLOR_ATTACHMENTS,
1237 LIMIT_MAX_TEXTURES_PER_UNIFORM_SET,
1238 LIMIT_MAX_SAMPLERS_PER_UNIFORM_SET,
1239 LIMIT_MAX_STORAGE_BUFFERS_PER_UNIFORM_SET,
1240 LIMIT_MAX_STORAGE_IMAGES_PER_UNIFORM_SET,
1241 LIMIT_MAX_UNIFORM_BUFFERS_PER_UNIFORM_SET,
1242 LIMIT_MAX_DRAW_INDEXED_INDEX,
1243 LIMIT_MAX_FRAMEBUFFER_HEIGHT,
1244 LIMIT_MAX_FRAMEBUFFER_WIDTH,
1245 LIMIT_MAX_TEXTURE_ARRAY_LAYERS,
1246 LIMIT_MAX_TEXTURE_SIZE_1D,
1247 LIMIT_MAX_TEXTURE_SIZE_2D,
1248 LIMIT_MAX_TEXTURE_SIZE_3D,
1249 LIMIT_MAX_TEXTURE_SIZE_CUBE,
1250 LIMIT_MAX_TEXTURES_PER_SHADER_STAGE,
1251 LIMIT_MAX_SAMPLERS_PER_SHADER_STAGE,
1252 LIMIT_MAX_STORAGE_BUFFERS_PER_SHADER_STAGE,
1253 LIMIT_MAX_STORAGE_IMAGES_PER_SHADER_STAGE,
1254 LIMIT_MAX_UNIFORM_BUFFERS_PER_SHADER_STAGE,
1255 LIMIT_MAX_PUSH_CONSTANT_SIZE,
1256 LIMIT_MAX_UNIFORM_BUFFER_SIZE,
1257 LIMIT_MAX_VERTEX_INPUT_ATTRIBUTE_OFFSET,
1258 LIMIT_MAX_VERTEX_INPUT_ATTRIBUTES,
1259 LIMIT_MAX_VERTEX_INPUT_BINDINGS,
1260 LIMIT_MAX_VERTEX_INPUT_BINDING_STRIDE,
1261 LIMIT_MIN_UNIFORM_BUFFER_OFFSET_ALIGNMENT,
1262 LIMIT_MAX_COMPUTE_SHARED_MEMORY_SIZE,
1263 LIMIT_MAX_COMPUTE_WORKGROUP_COUNT_X,
1264 LIMIT_MAX_COMPUTE_WORKGROUP_COUNT_Y,
1265 LIMIT_MAX_COMPUTE_WORKGROUP_COUNT_Z,
1266 LIMIT_MAX_COMPUTE_WORKGROUP_INVOCATIONS,
1267 LIMIT_MAX_COMPUTE_WORKGROUP_SIZE_X,
1268 LIMIT_MAX_COMPUTE_WORKGROUP_SIZE_Y,
1269 LIMIT_MAX_COMPUTE_WORKGROUP_SIZE_Z,
1270 LIMIT_MAX_VIEWPORT_DIMENSIONS_X,
1271 LIMIT_MAX_VIEWPORT_DIMENSIONS_Y,
1272 LIMIT_SUBGROUP_SIZE,
1273 LIMIT_SUBGROUP_IN_SHADERS, // Set flags using SHADER_STAGE_VERTEX_BIT, SHADER_STAGE_FRAGMENT_BIT, etc.
1274 LIMIT_SUBGROUP_OPERATIONS,
1275 LIMIT_VRS_TEXEL_WIDTH,
1276 LIMIT_VRS_TEXEL_HEIGHT,
1277 };
1278
1279 virtual uint64_t limit_get(Limit p_limit) const = 0;
1280
1281 //methods below not exposed, used by RenderingDeviceRD
1282 virtual void prepare_screen_for_drawing() = 0;
1283
1284 virtual void swap_buffers() = 0;
1285
1286 virtual uint32_t get_frame_delay() const = 0;
1287
1288 virtual void submit() = 0;
1289 virtual void sync() = 0;
1290
1291 enum MemoryType {
1292 MEMORY_TEXTURES,
1293 MEMORY_BUFFERS,
1294 MEMORY_TOTAL
1295 };
1296
1297 virtual uint64_t get_memory_usage(MemoryType p_type) const = 0;
1298
1299 virtual RenderingDevice *create_local_device() = 0;
1300
1301 virtual void set_resource_name(RID p_id, const String p_name) = 0;
1302
1303 virtual void draw_command_begin_label(String p_label_name, const Color p_color = Color(1, 1, 1, 1)) = 0;
1304 virtual void draw_command_insert_label(String p_label_name, const Color p_color = Color(1, 1, 1, 1)) = 0;
1305 virtual void draw_command_end_label() = 0;
1306
1307 virtual String get_device_vendor_name() const = 0;
1308 virtual String get_device_name() const = 0;
1309 virtual RenderingDevice::DeviceType get_device_type() const = 0;
1310 virtual String get_device_api_version() const = 0;
1311 virtual String get_device_pipeline_cache_uuid() const = 0;
1312
1313 virtual uint64_t get_driver_resource(DriverResource p_resource, RID p_rid = RID(), uint64_t p_index = 0) = 0;
1314
1315 static RenderingDevice *get_singleton();
1316 RenderingDevice();
1317
1318protected:
1319 static const char *shader_stage_names[RenderingDevice::SHADER_STAGE_MAX];
1320
1321 static const uint32_t MAX_UNIFORM_SETS = 16;
1322
1323 //binders to script API
1324 RID _texture_create(const Ref<RDTextureFormat> &p_format, const Ref<RDTextureView> &p_view, const TypedArray<PackedByteArray> &p_data = Array());
1325 RID _texture_create_shared(const Ref<RDTextureView> &p_view, RID p_with_texture);
1326 RID _texture_create_shared_from_slice(const Ref<RDTextureView> &p_view, RID p_with_texture, uint32_t p_layer, uint32_t p_mipmap, uint32_t p_mipmaps = 1, TextureSliceType p_slice_type = TEXTURE_SLICE_2D);
1327 Ref<RDTextureFormat> _texture_get_format(RID p_rd_texture);
1328
1329 FramebufferFormatID _framebuffer_format_create(const TypedArray<RDAttachmentFormat> &p_attachments, uint32_t p_view_count);
1330 FramebufferFormatID _framebuffer_format_create_multipass(const TypedArray<RDAttachmentFormat> &p_attachments, const TypedArray<RDFramebufferPass> &p_passes, uint32_t p_view_count);
1331 RID _framebuffer_create(const TypedArray<RID> &p_textures, FramebufferFormatID p_format_check = INVALID_ID, uint32_t p_view_count = 1);
1332 RID _framebuffer_create_multipass(const TypedArray<RID> &p_textures, const TypedArray<RDFramebufferPass> &p_passes, FramebufferFormatID p_format_check = INVALID_ID, uint32_t p_view_count = 1);
1333 RID _sampler_create(const Ref<RDSamplerState> &p_state);
1334 VertexFormatID _vertex_format_create(const TypedArray<RDVertexAttribute> &p_vertex_formats);
1335 RID _vertex_array_create(uint32_t p_vertex_count, VertexFormatID p_vertex_format, const TypedArray<RID> &p_src_buffers, const Vector<int64_t> &p_offsets = Vector<int64_t>());
1336
1337 Ref<RDShaderSPIRV> _shader_compile_spirv_from_source(const Ref<RDShaderSource> &p_source, bool p_allow_cache = true);
1338 Vector<uint8_t> _shader_compile_binary_from_spirv(const Ref<RDShaderSPIRV> &p_bytecode, const String &p_shader_name = "");
1339 RID _shader_create_from_spirv(const Ref<RDShaderSPIRV> &p_spirv, const String &p_shader_name = "");
1340
1341 RID _uniform_set_create(const TypedArray<RDUniform> &p_uniforms, RID p_shader, uint32_t p_shader_set);
1342
1343 Error _buffer_update(RID p_buffer, uint32_t p_offset, uint32_t p_size, const Vector<uint8_t> &p_data, BitField<BarrierMask> p_post_barrier = BARRIER_MASK_ALL_BARRIERS);
1344
1345 RID _render_pipeline_create(RID p_shader, FramebufferFormatID p_framebuffer_format, VertexFormatID p_vertex_format, RenderPrimitive p_render_primitive, const Ref<RDPipelineRasterizationState> &p_rasterization_state, const Ref<RDPipelineMultisampleState> &p_multisample_state, const Ref<RDPipelineDepthStencilState> &p_depth_stencil_state, const Ref<RDPipelineColorBlendState> &p_blend_state, BitField<PipelineDynamicStateFlags> p_dynamic_state_flags, uint32_t p_for_render_pass, const TypedArray<RDPipelineSpecializationConstant> &p_specialization_constants);
1346 RID _compute_pipeline_create(RID p_shader, const TypedArray<RDPipelineSpecializationConstant> &p_specialization_constants);
1347
1348 DrawListID _draw_list_begin(RID p_framebuffer, InitialAction p_initial_color_action, FinalAction p_final_color_action, InitialAction p_initial_depth_action, FinalAction p_final_depth_action, const Vector<Color> &p_clear_color_values = Vector<Color>(), float p_clear_depth = 1.0, uint32_t p_clear_stencil = 0, const Rect2 &p_region = Rect2(), const TypedArray<RID> &p_storage_textures = TypedArray<RID>());
1349 Vector<int64_t> _draw_list_begin_split(RID p_framebuffer, uint32_t p_splits, InitialAction p_initial_color_action, FinalAction p_final_color_action, InitialAction p_initial_depth_action, FinalAction p_final_depth_action, const Vector<Color> &p_clear_color_values = Vector<Color>(), float p_clear_depth = 1.0, uint32_t p_clear_stencil = 0, const Rect2 &p_region = Rect2(), const TypedArray<RID> &p_storage_textures = TypedArray<RID>());
1350 void _draw_list_set_push_constant(DrawListID p_list, const Vector<uint8_t> &p_data, uint32_t p_data_size);
1351 void _compute_list_set_push_constant(ComputeListID p_list, const Vector<uint8_t> &p_data, uint32_t p_data_size);
1352 Vector<int64_t> _draw_list_switch_to_next_pass_split(uint32_t p_splits);
1353
1354 struct SpirvReflectionData {
1355 BitField<ShaderStage> stages_mask;
1356 uint32_t vertex_input_mask;
1357 uint32_t fragment_output_mask;
1358 bool is_compute;
1359 uint32_t compute_local_size[3];
1360 uint32_t push_constant_size;
1361 BitField<ShaderStage> push_constant_stages_mask;
1362
1363 struct Uniform {
1364 UniformType type;
1365 uint32_t binding;
1366 BitField<ShaderStage> stages_mask;
1367 uint32_t length; // Size of arrays (in total elements), or ubos (in bytes * total elements).
1368 bool writable;
1369 };
1370 Vector<Vector<Uniform>> uniforms;
1371
1372 struct SpecializationConstant {
1373 PipelineSpecializationConstantType type;
1374 uint32_t constant_id;
1375 union {
1376 uint32_t int_value;
1377 float float_value;
1378 bool bool_value;
1379 };
1380 BitField<ShaderStage> stages_mask;
1381 };
1382 Vector<SpecializationConstant> specialization_constants;
1383 };
1384
1385 Error _reflect_spirv(const Vector<ShaderStageSPIRVData> &p_spirv, SpirvReflectionData &r_reflection_data);
1386};
1387
1388VARIANT_ENUM_CAST(RenderingDevice::DeviceType)
1389VARIANT_ENUM_CAST(RenderingDevice::DriverResource)
1390VARIANT_ENUM_CAST(RenderingDevice::ShaderStage)
1391VARIANT_ENUM_CAST(RenderingDevice::ShaderLanguage)
1392VARIANT_ENUM_CAST(RenderingDevice::CompareOperator)
1393VARIANT_ENUM_CAST(RenderingDevice::DataFormat)
1394VARIANT_BITFIELD_CAST(RenderingDevice::BarrierMask);
1395VARIANT_ENUM_CAST(RenderingDevice::TextureType)
1396VARIANT_ENUM_CAST(RenderingDevice::TextureSamples)
1397VARIANT_BITFIELD_CAST(RenderingDevice::TextureUsageBits)
1398VARIANT_ENUM_CAST(RenderingDevice::TextureSwizzle)
1399VARIANT_ENUM_CAST(RenderingDevice::TextureSliceType)
1400VARIANT_ENUM_CAST(RenderingDevice::SamplerFilter)
1401VARIANT_ENUM_CAST(RenderingDevice::SamplerRepeatMode)
1402VARIANT_ENUM_CAST(RenderingDevice::SamplerBorderColor)
1403VARIANT_ENUM_CAST(RenderingDevice::VertexFrequency)
1404VARIANT_ENUM_CAST(RenderingDevice::IndexBufferFormat)
1405VARIANT_BITFIELD_CAST(RenderingDevice::StorageBufferUsage)
1406VARIANT_ENUM_CAST(RenderingDevice::UniformType)
1407VARIANT_ENUM_CAST(RenderingDevice::RenderPrimitive)
1408VARIANT_ENUM_CAST(RenderingDevice::PolygonCullMode)
1409VARIANT_ENUM_CAST(RenderingDevice::PolygonFrontFace)
1410VARIANT_ENUM_CAST(RenderingDevice::StencilOperation)
1411VARIANT_ENUM_CAST(RenderingDevice::LogicOperation)
1412VARIANT_ENUM_CAST(RenderingDevice::BlendFactor)
1413VARIANT_ENUM_CAST(RenderingDevice::BlendOperation)
1414VARIANT_BITFIELD_CAST(RenderingDevice::PipelineDynamicStateFlags)
1415VARIANT_ENUM_CAST(RenderingDevice::PipelineSpecializationConstantType)
1416VARIANT_ENUM_CAST(RenderingDevice::InitialAction)
1417VARIANT_ENUM_CAST(RenderingDevice::FinalAction)
1418VARIANT_ENUM_CAST(RenderingDevice::Limit)
1419VARIANT_ENUM_CAST(RenderingDevice::MemoryType)
1420VARIANT_ENUM_CAST(RenderingDevice::Features)
1421
1422typedef RenderingDevice RD;
1423
1424#endif // RENDERING_DEVICE_H
1425